Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Registers Overview and Configuration Process
78
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
• Devices that are hidden from host configuration space via the DEVHIDE register are 
not hidden from the configuration space as seen from the JTAG/SMBus/PECI port of 
an IIO. All PCI devices are always visible via JTAG/SMBus/PECI.
• Devices or functions when turned off are always hidden (and not programmable to 
be unhidden) from host configuration space and also from JTAG/SMBus/PECI.
• Devices that are not turned off, but are otherwise not used in a given platform 
configuration can be hidden from host configuration space by BIOS appropriately 
programming the DEVHIDE register.
• The only change DEVHIDE register makes is to abort Type0 configuration accesses 
to the device space itself.
12.2.1.6
CSR Access Via PECI
CSR access via PECI will use the hardcode Bus 0 and Bus 1 and not use the value in 
CPUBUSNO(0) and CPUBUSNO(1).
CSR read via PECI is always allowed. 
CSR write via PECI to RW_LB registers is allowed in the following cases:
• In BMC_INIT mode, the CSR write via PECI is allowed unconditionally. 
• If not in BMC_INIT mode, the CSR write via PECI is allowed to a subset of RW_LB 
registers after BIOS sets the “PECI is Trusted bit” in related PCU register. For the 
subset of the CSRs, refer to the following. 
Table 12-2. RW_LB CSRs list allowed PECI write when not in BMC_INIT mode
Device Range
Function Range
Offset Range
Min
Max
0
0
000h
FFFh
2, 3
0, 1, 2, 3
000h
FFFh
4
0, 1, 2, 3, 4, 5, 6, 7
000h
FFFh
5
0, 1, 2, 4
000h
FFFh
8, 9, 24
0
0FCh
0FFh
8, 9, 24
3
12Ch
130h
15
0
104h
1AFh
15
1
080h
0CFh
16
0, 1, 4, 5
104h
18Bh
16
0, 1, 4, 5
1F4h
1FFh
16
2, 3, 6, 7
104h
147h
16
2, 6
308h
418h
16
2, 6
608h
610h
29
0
104h
1AFh
29
1
080h
0CFh
30
0, 1, 4, 5
104h
18Bh
30
0, 1, 4, 5
1F4h
1FFh
30
2, 3, 6, 7
104h
147h
30
2, 6
308h
418h
30
2, 6
608h
610h
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