Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
84
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.1.2
DID
13.1.3
PCICMD
Type:
CFG
PortID:
N/A
Bus:
1
Offset:
0x2
15:0
RO
Varies
Device Identification Number (device_identification_number):
Device ID values vary from function to function. Bits 15:8 are equal to 
0xE. Refer to 
 for the DID of each device.
Type:
CFG
PortID:
N/A
Bus:
1
Offset:
0x4
Bit
Attr
Default
Description
15:11
RV
-
Reserved.
10:10
RO
0x0
INTx Disable (intx_disable):
N/A for these devices
9:9
RO
0x0
Fast Back-to-Back Enable (fast_back_to_back_enable):
Not applicable to PCI Express and is hardwired to 0
8:8
RO
0x0
SERR Enable (serr_enable):
This bit has no impact on error reporting from these devices
7:7
RO
0x0
IDSEL Stepping/Wait Cycle Control (idsel_stepping_wait_cycle_control):
Not applicable to internal devices. Hardwired to 0.
6:6
RO
0x0
Parity Error Response (parity_error_response):
This bit has no impact on error reporting from these devices
5:5
RO
0x0
VGA palette snoop Enable (vga_palette_snoop_enable):
Not applicable to internal devices. Hardwired to 0.
4:4
RO
0x0
Memory Write and Invalidate Enable (memory_write_and_invalidate_enable):
Not applicable to internal devices. Hardwired to 0.
3:3
RO
0x0
Special Cycle Enable (special_cycle_enable):
Not applicable. Hardwired to 0.
2:2
RO
0x0
Bus Master Enable (bus_master_enable):
Hardwired to 0 since these devices don't generate any transactions
1:1
RO
0x0
Memory Space Enable (memory_space_enable):
Hardwired to 0 since these devices don't decode any memory BARs
0:0
RO
0x0
IO Space Enable (io_space_enable):
Hardwired to 0 since these devices don't decode any IO BARs
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