Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
85
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.1.4
PCISTS
Type:
CFG
PortID:
N/A
Bus:
1
Offset:
0x6
Bit
Attr
Default
Description
15:15
RO
0x0
Detected Parity Error (detected_parity_error):
This bit is set when the device receives a packet on the primary side with an 
uncorrectable data error including a packet with poison bit set or an 
uncorrectable address / control parity error. The setting of this bit is 
regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 
R2PCIe will never set this bit.
14:14
RO
0x0
Signaled System Error (signaled_system_error):
Hardwired to 0
13:13
RO
0x0
Received Master Abort (received_master_abort):
Hardwired to 0
12:12
RO
0x0
Received Target Abort (received_target_abort):
Hardwired to 0
11:11
RO
0x0
Signaled Target Abort (signaled_target_abort):
Hardwired to 0
10:9
RO
0x0
DEVSEL# Timing (devsel_timing):
Not applicable to PCI Express. Hardwired to 0.
8:8
RO
0x0
Master Data Parity Error (master_data_parity_error):
Hardwired to 0
7:7
RO
0x0
Fast Back-to-Back (fast_back_to_back):
Not applicable to PCI Express. Hardwired to 0.
6:6
RV
-
Reserved (reserved):
5:5
RO
0x0
pci66MHz capable (pci66mhz_capable):
Not applicable to PCI Express. Hardwired to 0.
4:4
RO
0x1
Capabilities List (capabilities_list):
This bit indicates the presence of a capabilities list structure
3:3
RO
0x0
INTx Status (intx_status):
Hardwired to 0
2:0
RV
-
Reserved.
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