Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
89
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.1.16 MINGNT
13.1.17 MAXLAT
13.2
Integrated Memory Controller (iMC) Configuration 
Registers
Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family has two integrated 
Memory Controllers. Device 15 and 16 address iMC 0 and Device 29 and 30 address 
iMC 1. Each Memory Controller has four DDR3 Channels. 
Type:
CFG
PortID:
N/A
Bus:
1
Offset:
0x3e
Bit
Attr
Default
Description
7:0
RO
0x0
Minimum Grant Value (mgv):
Not applicable and hardwired to 0.
Type:
CFG
PortID:
N/A
Bus:
1
Offset:
0x3f
Bit
Attr
Default
Description
7:0
RO
0x0
Maximum Latency Value (mlv):
Not applicable and hardwired to 0.
Bus
Device
Function
Memory Channel
Comments
1
15
2
3
4
5
Memory Channel 0
Memory Channel 1
Memory Channel 2
Memory Channel 3
iMC 0 Target Address Decode, Channels 
Rank and Memory Timing Registers
1
16
4
5
0
1
Memory Channel 0
Memory Channel 1
Memory Channel 2
Memory Channel 3
iMC 0 Thermal Control Registers
1
16
6
7
2
3
Memory Channel 0
Memory Channel 1
Memory Channel 2
Memory Channel 3
iMC 0 Test Registers
1
29
2
3
4
5
Memory Channel 0
Memory Channel 1
Memory Channel 2
Memory Channel 3
iMC 1 Target Address Decode, Channels 
Rank and Memory Timing registers
1
30
4
5
0
1
Memory Channel 0
Memory Channel 1
Memory Channel 2
Memory Channel 3
iMC 1 Thermal Control Registers
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