Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
91
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.1
PXPCAP
PCI Express Capability.
MCMTR2
0xb0
32
MC_INIT_STATE_G
0xb4
32
RCOMP_TIMER
0xc0
32
PXPENHCAP
0x100
32
MH_MAINCNTL
0x104
32
MH_SENSE_500NS_CFG
0x10c
32
MH_DTYCYC_MIN_ASRT_CNTR_0
0x110
32
MH_DTYCYC_MIN_ASRT_CNTR_1
0x114
32
MH_IO_500NS_CNTR
0x118
32
MH_CHN_ASTN
0x11c
32
MH_TEMP_STAT
0x120
32
MH_EXT_STAT
0x124
32
SMB_STAT_0
0x180
32
SMBCMD_0
0x184
32
SMBCNTL_0
0x188
32
SMB_TSOD_POLL_RATE_CNTR_0
0x18c
32
SMB_STAT_1
0x190
32
SMBCMD_1
0x194
32
SMBCNTL_1
0x198
32
SMB_TSOD_POLL_RATE_CNTR_1
0x19c
32
SMB_PERIOD_CFG
0x1a0
32
SMB_PERIOD_CNTR
0x1a4
32
SMB_TSOD_POLL_RATE
0x1a8
32
Register name
Offset
Size
Type:
CFG
PortID:
N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x40
Bit
Attr
Default
Description
31:30
RV
-
Reserved.
29:25
RO
0x0
Interrupt Message Number (interrupt_message_number):
N/A for this device
24:24
RO
0x0
Slot Implemented (slot_implemented):
N/A for integrated endpoints
23:20
RO
0x9
Device/Port Type (device_port_type):
Device type is Root Complex Integrated Endpoint
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