Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
94
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
For 1-way interleave, channel 1-3 mirror pair: target list = <1,3,x,x>, TAD ways = 
“00”
For 2-way interleave, 0-2 mirror pair and 1-3 mirror pair: target list = <0,1,2,3>, TAD 
ways = “01”
For 1-way interleave, lockstep + mirroring, target list = <0,2,x,x>, TAD ways = “00”
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x80, 0x84, 0x88, 0x8c, 0x90, 0x94, 0x98, 0x9c, 0xa0, 0xa4, 0xa8, 0xac
Bit
Attr
Default
Description
31:12
RW_LB
0x0
TAD_LIMIT (tad_limit):
highest address of the range in system address space, 64MB granularity, 
i.e. TADRANGLIMIT[45:26].
11:10
RW_LB
0x0
TAD_SKT_WAY (tad_skt_way):
socket interleave wayness
00 = 1 way,
01 = 2 way,
10 = 4 way,
11 = 8 way.
9:8
RW_LB
0x0
TAD_CH_WAY (tad_ch_way):
channel interleave wayness
00 - interleave across 1 channel or mirror pair
01 - interleave across 2 channels or mirror pairs
10 - interleave across 3 channels
11 - interleave across 4 channels
This parameter effectively tells iMC how much to divide the system address 
by when adjusting for the channel interleave. Since both channels in a pair 
store every line of data, divide by 1 when interleaving across one pair and 2 
when interleaving across two pairs. For HA, it tells how may channels to 
distribute the read requests across. When interleaving across 1 pair, this 
distributes the reads to two channels, when interleaving across 2 pairs, this 
distributes the reads across 4 pairs. Writes always go to both channels in 
the pair when the read target is either channel.
7:6
RW_LB
0x0
TAD_CH_TGT3 (tad_ch_tgt3):
target channel for channel interleave 3 (used for 4-way TAD interleaving).
This register is used in the iMC only for reverse address translation for 
logging spare/patrol errors, converting a rank address back to a system 
address.
5:4
RW_LB
0x0
TAD_CH_TGT2 (tad_ch_tgt2):
target channel for channel interleave 2 (used for 3/4-way TAD interleaving).
3:2
RW_LB
0x0
TAD_CH_TGT1 (tad_ch_tgt1):
target channel for channel interleave 1 (used for 2/3/4-way TAD 
interleaving).
1:0
RW_LB
0x0
TAD_CH_TGT0 (tad_ch_tgt0):
target channel for channel interleave 0 (used for 1/2/3/4-way TAD 
interleaving).
downloadlike
ArtboardArtboardArtboard
Report Bug