Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
95
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.4
MCMTR2
MC Memory Technology Register 2
13.2.1.5
MC_INIT_STATE_G
Initialization state for boot, training and IOSAV.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0xb0
Bit
Attr
Default
Description
31:4
RV
-
Reserved.
3:0
RW_L
0x0
MONROE_CHN_FORCE_SR (monroe_chn_force_sr):
Monroe Technology software channel force SRcontrol. When set, the 
corresponding channel is ignoring the ForceSRExit. A new transaction arrive at 
this channel will still cause the SR exit.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0xb4
Bit
Attr
Default
Description
31:15
RV
-
Reserved.
14:14
RWS_L
0x0
reset_io_vmse_rhs:
Training Reset for DDRIO. It resets TX/RX FIFO pointers and some read related 
FSMs inside MCIO. This signal goes to VMSE channel 1 on Intel Xeon processor 
E7 v2 Series-based platform. Make sure this bit is cleared before enabling 
DDRIO in VMSE mode.
13:13
RWS_L
0x0
reset_vmse2to1:
This is actually a DDRIO reset control, which will reset entire MCIO logic except 
CSRs. One usage model is to set up VMSE 2:1 mode correctly in DDRIO. The 
register must be set and reset after the IMC mode register is configured to 
VMSE 2:1 mode.
12:9
RWS_L
0x0
cs_oe_en:
8:8
RWS_L
0x1
MC is in SR (safe_sr):
This bit indicates if it is safe to keep the MC in SR during MC-reset. If it is clear 
when reset occurs, it means that the reset is without warning and the DDR-
reset should be asserted. If set when reset occurs, it indicates that DDR is 
already in SR and it can keep it this way. This bit can also indicate MRC if reset 
without warning has occurred, and if it has, cold-reset flow should be selected.
BIOS need to clear this bit at MRC entry.
7:7
RW_L
0x0
MRC_DONE (mrc_done):
This bit indicates the PCU that the MRC is done, MC is in normal mode, ready to 
serve
MRC should set this bit when MRC is done, but it doesn’t need to wait until 
training results are saved in BIOS flash.
6:6
RV
-
Reserved2:
Reserved.
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