Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
97
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.1.7
PXPENHCAP
This field points to the next Capability in extended configuration space.
13.2.1.8
MH_MAINCNTL
MEMHOT Main Control.
21:21
RW
0x0
ignore_mdll_locked_bit:
Ignore DDRIO MDLL lock status during rcomp when set
20:20
RW
0x0
no_mdll_fsm_override:
Do not force DDRIO MDLL on during rcomp when set
19:17
RV
-
Reserved.
16:16
RW_LV
0x0
First RCOMP has been done in DDRIO (first_rcomp_done):
This is a status bit that indicates the first RCOMP has been completed. It is 
cleared on reset, and set by MC HW when the first RCOMP is completed. BIOS 
should wait until this bit is set before executing any DDR command.
15:0
RW
0xc00
COUNT (count):
DCLK cycle count that MC needs to wait from the point it has triggered RCOMP 
evaluation until it can trigger the load to registers.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0xc0
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x100
Bit
Attr
Default
Description
31:20
RO
0x0
Next Capability Offset (next_capability_offset):
Indicates there are no capability structures in the enhanced configuration 
space.
19:16
RO
0x1
Capability Version (capability_version):
Capability Version.
15:0
RO
0xb
Capability ID (capability_id):
Capability ID.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x104
Bit
Attr
Default
Description
31:19
RV
-
Reserved.
18:18
RW
0x0
MHOT_SMI_EN (mhot_smi_en):
Generate SMI during internal MEM_HOT# event assertion
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