Intel E7-8890 v2 CM8063601213513 User Manual
Product codes
CM8063601213513
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
297
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.2.124 XPPMEVH[0:1]
XP PM Events High
Selections in this register correspond to fields within the PEX packet header. Each field
selection is ANDed with all other fields in this register including the XPPMEVL except for
the Global Event signals. These signals are OR’ed with any event in the XPPMEVL and
enables for debug operations requiring the accumulation of specific debug signals.The
qualifications for fields in this register are as follows:
selection is ANDed with all other fields in this register including the XPPMEVL except for
the Global Event signals. These signals are OR’ed with any event in the XPPMEVL and
enables for debug operations requiring the accumulation of specific debug signals.The
qualifications for fields in this register are as follows:
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x4a4, 0x4a8
Bit
Attr
Default
Description
31:8
RV
-
Reserved
7:2
RW
0x0
global_event_selection:
Global Event Selection
Selects which GE[3:0] is used for event counting. This field is OR’d with other
Selects which GE[3:0] is used for event counting. This field is OR’d with other
fields in this register. The GEs cannot be qualified with other PerfMon signals.If
more than 1 GE is selected then the resultant event is the OR between each GE.
However, properly counting Global Event based on design, XP PM Response
However, properly counting Global Event based on design, XP PM Response
Control Register bit [13:11] CENS must be set to choose GE[3:0] and also
bit[18:17] CNTEVSEL must be set to 2’b10.
1x_xxxx: GE[5]
x1_xxxx: GE[4]
xx_1xxx: GE[3]
xx_x1xx: GE[2]
xx_xx1x: GE[1]
xx_xxx1: GE[0]
1x_xxxx: GE[5]
x1_xxxx: GE[4]
xx_1xxx: GE[3]
xx_x1xx: GE[2]
xx_xx1x: GE[1]
xx_xxx1: GE[0]
1:0
RW
0x0
inbound_or_outbound_selection
Inbound or Outbound Selection
Selects which path to count transactions.
1x: Outbound
x1: Inbound (from PCI bus)
11: Either
Selects which path to count transactions.
1x: Outbound
x1: Inbound (from PCI bus)
11: Either