AMD Athlon 64 Quad FX72/ 2.8GHz/ PIB ADAFX72DIBOX Product Datasheet

Compatible with Existing 32-Bit Code Base
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Including support for SSE, SSE2, SSE3

*

, MMX™, 

3DNow!™ technology and legacy x86 instructions 

*

SSE3 supported by Rev. E and later processors

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Runs existing operating systems and drivers

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Local APIC on-chip

AMD64 Technology
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AMD64 technology instruction set extensions

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64-bit integer registers, 48-bit virtual addresses, 
40-bit physical addresses

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Eight additional 64-bit integer registers (16 total)

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Eight additional 128-bit SSE/SSE2/SSE3 registers 

(16 total)

Multi-Core Architecture
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Single-core or dual-core options

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Discrete L1 and L2 cache structures for each core

64-Kbyte 2-Way Associative ECC-Protected 
L1 Data Cache
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Two 64-bit operations per cycle, 3-cycle latency

64-Kbyte 2-Way Associative Parity-Protected 
L1 Instruction Cache
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With advanced branch prediction

16-Way Associative ECC-Protected L2 Cache
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Exclusive cache architecture—storage in addition 

to L1 caches

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Up to 1 Mbyte per L2 cache

Machine Check Architecture
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Includes hardware scrubbing of major ECC-
protected arrays

Power Management
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Multiple low-power states

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System Management Mode (SMM)

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ACPI compliant, including support for processor 
performance states in some models

Packaging
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940-pin lidded ceramic micro PGA

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1.27-mm pin pitch

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31x31-row pin array

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40mm x 40mm ceramic substrate

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Ceramic C4 die attach

Integrated Memory Controller
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Low-latency, high-bandwidth

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144-bit DDR SDRAM at 100, 133, 166, and 
200 MHz

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Supports up to eight registered DIMMs

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ECC checking with double-bit detect and single-bit 
correct

Electrical Interfaces
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HyperTransport™ technology: LVDS-like 
differential, unidirectional

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DDR SDRAM: SSTL_2 per JEDEC specification

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Clock, reset, and test signals also use DDR 
SDRAM-like electrical specifications.

HyperTransport™ Technology to I/O Devices
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One 16-bit link supporting speeds up to 800 MHz 
(1600 MT/s) or 3.2 Gigabytes/s in each direction

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