Kingston Technology 1GB(2 x 512MB), 1066MHz,SDRAM-DDR2, 2.2V, Gold, CL5 (5-5-5-15), DIMM 240-pin KHX8500D2K2/1GN Data Sheet
Product codes
KHX8500D2K2/1GN
Memory Module Specification
Document No. 4804670-001.B00
09/23/08
KHX8500D2K2/1GN
1GB (512MB 64M x 64-Bit x 2 pcs.)
PC2-8500 CL5 240-Pin DIMM Kit
Page 1
T E C H N O L O G Y
T
E
C
H
N
O
L
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G
Y
Keyed
DESCRIPTION:
Kingston's KHX8500D2K2/1GN is a kit of two 64M x 64-bit (512MB) DDR2-1066 CL5 SDRAM
(Synchronous DRAM) "NVIDIA SLI-Ready" memory modules, based on eight 64M x 8-bit DDR2
FBGA components per module. Total kit capacity is 1GB (1024MB). Each module pair has been
tested to run at DDR2- 1066MHz at a latency timing of 5-5-5-15 at 2.2V. The SPD is programmed
to JEDEC standard latency 800Mhz timing of 5-5-5-18 at 1.8V. Each 240-pin DIMM uses gold
contact fingers and requires +1.8V. The electrical and mechanical specifications are as follows:
(Synchronous DRAM) "NVIDIA SLI-Ready" memory modules, based on eight 64M x 8-bit DDR2
FBGA components per module. Total kit capacity is 1GB (1024MB). Each module pair has been
tested to run at DDR2- 1066MHz at a latency timing of 5-5-5-15 at 2.2V. The SPD is programmed
to JEDEC standard latency 800Mhz timing of 5-5-5-18 at 1.8V. Each 240-pin DIMM uses gold
contact fingers and requires +1.8V. The electrical and mechanical specifications are as follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-18 at +1.8V / 5-5-5-15 at +2.2V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 5-5-5-18 at +1.8V / 5-5-5-15 at +2.2V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.180” (30.00mm), single sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
51.5ns (min.)
Refresh to Active/Refresh Command Time (tRFC)
105ns
Row Active Time (tRAS)
39ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
1.018 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C