Intel J1750 FH8065301562600 User Manual

Intel

Product codes

FH8065301562600

Datasheet

1125

PCU – System Management Bus (SMBus)

22.8

PCU SMBus I/O Registers

Table 166.

Summary of PCU SMBus I/O Registers—SMB_Config_IOBAR

Offset

Size

Register ID—Description

Default

Value

0h

1

“Host Status Register (SMB_Mem_HSTS_io)—Offset 0h” on page 1126

00h

2h

1

“Host Control Register (SMB_Mem_HCTL_io)—Offset 2h” on page 1127

00h

3h

1

“Host Command Register (SMB_Mem_HCMD_io)—Offset 3h” on page 1129

00h

4h

1

“Transmit Slave Address Register (SMB_Mem_TSA_io)—Offset 4h” on page 1129

00h

5h

1

“Data 0 Register (SMB_Mem_HD0_io)—Offset 5h” on page 1130

00h

6h

1

“Data 1 Register (SMB_Mem_HD1_io)—Offset 6h” on page 1130

00h

7h

1

“Host Block Data (SMB_Mem_HBD_io)—Offset 7h” on page 1131

00h

8h

1

“Packet Error Check Data Register (SMB_Mem_PEC_io)—Offset 8h” on page 1132

00h

Ch

1

“Auxiliary Status (SMB_Mem_AUXS_io)—Offset Ch” on page 1132

00h

Dh

1

“Auxiliary Control (SMB_Mem_AUXC_io)—Offset Dh” on page 1133

00h

Fh

1

“SMBUS_PIN_CTL Register (SMB_Mem_SMBC_io)—Offset Fh” on page 1133

07h

10h

1

“Slave Status Register (SMB_Mem_SSTS_io)—Offset 10h” on page 1134

00h

11h

1

“Slave Command Register (SMB_Mem_SCMD_io)—Offset 11h” on page 1135

00h

14h

1

“Notify Device Address Register (SMB_Mem_NDA_io)—Offset 14h” on page 1136

00h

16h

1

“Notify Data Low Byte Register (SMB_Mem_NDLB_io)—Offset 16h” on page 1136

00h

17h

1

“Notify Data High Byte Register (SMB_Mem_NDHB_io)—Offset 17h” on page 1137

00h