Intel J1750 FH8065301562600 User Manual

Datasheet

1269

Slave Initialization Command Word 3

Default: 00h

4:3

X

WO

OCW2S: OCW2 Select: When selecting OCW2, bits 4:3 = 00

2:0

X

WO

ILS: Interrupt Level Select (L2, L1, L0): L2, L1, and L0 determine the interrupt level 

acted upon when the SL bit is active. A simple binary code, outlined above, selects the 

channel for the command to act upon. When the SL bit is inactive, these bits do not 

have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. Bits 

Interrupt Level Bits Interrupt Level 000 IRQ0/8 100 IRQ4/12 001 IRQ1/9 101 IRQ5/13 

010 IRQ2/10 110 IRQ6/14 011 IRQ3/11 111 IRQ7/15

Type: I/O Register

(Size: 8 bits)

7

4

0

0

0

0

0

0

0

0

0

MB

Z

CC

C

MB

Z

1

7:3

X

WO

MBZ: These bits must be programmed to zero.

2

X

WO

CCC: Cascaded Controller Connection (CCC): This bit must always be programmed to a 

1 to indicate the slave controller for interrupts 8 15 is cascaded on IRQ2.

1:0

X

WO

MBZ (MBZ1): These bits must be programmed to zero.