Intel D845GEBV2 BLKD845GERG2-10PK User Manual

Product codes
BLKD845GERG2-10PK
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Intel Desktop Board D845GEBV2/D845GERG2 Technical Product Specification 
110 
 
4.4.9  Chipset Configuration Submenu 
To access this menu, select Advanced on the menu bar and then Chipset Configuration. 
 
Maintenance 
Main 
Advanced  Security 
Power 
Boot 
Exit 
 PCI 
Configuration 
 Boot 
Configuration 
 
Peripheral Configuration 
 
IDE Configuration 
 
Diskette Configuration 
 
Event Log Configuration 
 
Video Configuration 
 
USB Configuration 
 
Chipset Configuration 
 
Fan Control Configuration 
The submenu represented in Table 65 is for configuring the chipset options. 
Table 65.  Chipset Configuration Submenu 
Feature Options 
Description 
ISA Enable Bit 
•  Enabled (default) 
•  Disabled 
When set to Enable, a PCI-to-PCI bridge will only 
recognize I/O addresses that do not alias to an ISA 
range (within the bridge’s assigned I/O range). 
PCI Latency Timer 
•  32 (default) 
•  64 
•  96 
•  128 
•  160 
•  192 
•  224 
•  248 
Allows you to control the time (in PCI bus clock 
cycles) that an agent on the PC bus can hold the bus 
when another agent has requested the bus. 
Extended Configuration 
•  Default (default) 
•  User Defined 
Allows the setting of extended configuration options. 
SDRAM Frequency 
•  Auto (default) 
•  266 MHz 
•  333 MHz 
Allows override of detected memory frequency value. 
NOTE:  If SDRAM Frequency is changed, you must 
reboot for the change to take effect.  After changing 
this setting and rebooting, the System Memory 
Speed parameter in the Main menu will reflect the 
new value. 
SDRAM Timing Control 
•  Auto (default) 
•  Manual – Aggressive 
•  Manual – User Defined 
Auto = Timings will be programmed according to the 
memory detected. 
Manual – Aggressive = Selects most aggressive 
user-defined timings. 
Manual – User Defined = Allows manual override of 
detected SDRAM settings. 
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