Intel Celeron 360 HH80552RE099512 User Manual

67

DBR#

Output

DBR# (Debug Reset) is used only in processor systems where no 
debug port is implemented on the system board. DBR# is used by a 
debug port interposer so that an in-target probe can drive system 
reset. If a debug port is implemented in the system, DBR# is a no 
connect in the system. DBR# is not a processor signal.

DBSY#

Input/

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for 
driving data on the processor FSB to indicate that the data bus is in 
use. The data bus is released after DBSY# is de-asserted. This 
signal must connect the appropriate pins/lands on all processor FSB 
agents.

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction 
cannot be ensured in-order completion. Assertion of DEFER# is 
normally the responsibility of the addressed memory or input/output 
agent. This signal must connect the appropriate pins/lands of all 
processor FSB agents.

DP[3:0]#

Input/

Output

DP[3:0]# (Data parity) provide parity protection for the D[63:0]# 
signals. They are driven by the agent responsible for driving 
D[63:0]#, and must connect the appropriate pins/lands of all 
processor FSB agents.

DRDY#

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data 
transfer, indicating valid data on the data bus. In a multi-common 
clock data transfer, DRDY# may be de-asserted to insert idle clocks. 
This signal must connect the appropriate pins/lands of all processor 
FSB agents.

DSTBN[3:0]#

Input/

Output

DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. 

DSTBP[3:0]#

Input/

Output

DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.

FCx

Other

FC signals are signals that are available for compatibility with other 
processors. 

D[15:0]#, DBI0# 

DSTBN0#

D[31:16]#, DBI1# 

DSTBN1#

D[47:32]#, DBI2# 

DSTBN2#

D[63:48]#, DBI3# 

DSTBN3#

D[15:0]#, DBI0# 

DSTBP0#

D[31:16]#, DBI1# 

DSTBP1#

D[47:32]#, DBI2# 

DSTBP2#

D[63:48]#, DBI3# 

DSTBP3#