Intel E3-1241 v3 CM8064601575331 User Manual

V

IL

HPD Input Low Voltage

0.02

—

0.21

V

V

IH

HPD Input High Voltage

0.84

—

1.05

V

V

OL

eDP_DISP_UTIL Output Low Voltage

0.1*V

CC

—

—

V

V

OH

eDP_DISP_UTIL Output High Voltage

0.9*V

CC

—

—

V

R

UP

eDP_DISP_UTIL Internal pull-up

100

—

—

Ω

R

DOWN

eDP_DISP_UTIL Internal pull-down

100

—

—

Ω

Vaux(Tx)

Aux peak-to-peak voltage at

transmitting device

0.39

—

1.38

V

Vaux(Rx)

Aux peak-to-peak voltage at receiving

device

0.32

—

1.36

V

eDP_RCOMP
DP_RCOMP

COMP Resistance

24.75

25

25.25

Ω

Note: 1. COMP resistance is to VCOMP_OUT.

V

IL

Input Low Voltage

—

V

CCIO_OUT

* 0.3

V

2

V

IH

Input High Voltage

V

CCIO_OUT

* 0.7

—

V

2, 4

V

OL

Output Low Voltage

—

V

CCIO_OUT

 * 0.1

V

2

V

OH

Output High Voltage

V

CCIO_OUT

 * 0.9

—

V

2, 4

R

ON

Buffer on Resistance

23

73

Ω

-

I

LI

Input Leakage

Current

—

±150

μA

3

Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The V

CCIO_OUT

 referred to in these specifications refers to instantaneous VCCIO_OUT.

3. For VIN between “0” V and V

CCIO_OUT

. Measured when the driver is tri-stated.

4. V

IH

 and V

OH

 may experience excursions above V

CCIO_OUT

. However, input signal drivers must

comply with the signal quality specifications.

V

IL

Input Low Voltage (TAP, except

TCK)

—

V

CCIO_TERM

 * 0.6

V

2

V

IH

Input High Voltage (TAP, except

TCK)

V

CCIO_TERM

 * 0.72

—

V

2, 4

V

IL

Input Low Voltage (TCK)

—

V

CCIO_TERM

 * 0.4

V

2

V

IH

Input High Voltage (TCK)

V

CCIO_TERM

 * 0.8

—

V

2, 4

V

HYSTERESIS

Hysteresis Voltage

V

CCIO_TERM

 * 0.2

—

V

—

R

ON

Buffer on Resistance (TDO)

12

28

Ω

—

V

IL

Input Low Voltage (other GTL)

—

V

CCIO_TERM

 * 0.6

V

2

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

98

Order No.: 328907-001