Intel Phi 7120A SC7120A Data Sheet

Product codes
SC7120A
Page of 78
Intel
®
 Xeon Phi™ Coprocessor Datasheet
Document ID Number: 328209 003EN
46
4.1.1
PROCHOT_N (Pin B12)
System baseboard routing to the PROCHOT_N pin must take into consideration the 
following details:
• PROCHOT_N pin is driven by the +3.3V power rail.
• PROCHOT_N pin is connected to a pull-down of 100k-ohm on the card.
• The input signal arriving at the pin from the baseboard must meet the following 
characteristics:
— VIH(min)= 2.7V
— VIL(max)= 0.5V
— Rise/Fall times(max)= 240ns
• The baseboard implementation can choose to be either push-pull or open-drain. In 
particular, an open-drain implementation must provide a pull-up resistor of 
10k-ohm or less on the baseboard to counteract the pull-down on the card.
SMB_PCI_CLK
I/O
PCI Express* System Management Bus Clock: 
SMB_PCI_CLK is the 3.3-volt clock signal for the SMBus 
Interface, which is normally used for power and/or 
thermal management and for monitoring the card. 
SMB_PCI_DAT
I/O
PCI Express* System Management Bus Data: 
SMB_PCI_DAT is the 3.3-volt data signal for the SMBus 
Interface, which is normally used for power and/or 
thermal management and for monitoring the card.
PRSNT1_N, PRSNT2_N
S
Following PCI Express* specification, PRSNT1_N# (pin 
A1) is connected on the coprocessor card to PRSNT2_N 
(pin B81). Remaining PRSNT2_N pins (17, B31, B48) 
must be unconnected on the baseboard.
VCC3
P
+3.3V Supply: The positive 3.3-volt power supply to 
the PCI Express* card.
+12V
P
+12V Supply: The positive 12-volt power supply to the 
PCI Express* card.
V_3P3_PCIAUX
P
+3.3VAux Supply.
PROCHOT_N (pin B12)
I
On the Intel® Xeon Phi™ coprocessor, the SMC 
supports an external path from the baseboard to the 
card's B12 pin, which allows system agents such as 
BMC or ME to throttle the card in response to card 
thermal events (thermal throttling). Pin B12, defined as 
reserved in the PCI Express* specification, has been 
renamed PROCHOT_N on the Intel
®
 Xeon Phi™ 
coprocessor and is driven by 3.3V power. This pin is 
held in inactive-high state by the card SMC, and must 
be driven active-low by the baseboard to exert 
throttling. Se
 for details.
WAKE_N
Not 
Used
PCI Express* Wake Signal.
EXP_JTAG[5:1]
Not 
Used
PCI Express* JTAG Interface.
Table 4-1.
PCI Express* Connector Signals on the Intel® Xeon Phi™ Coprocessor
Signal Name
Signal 
Type
Description