Intel E3-1226 v3 CM8064601575206 User Manual

NCTF

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical

reserved, so the loss of the solder joint continuity at end of life conditions will not

affect the overall product functionality.

ODT

On-Die Termination

OLTM

Open Loop Thermal Management

PCG

Platform Compatibility Guide (PCG) (previously known as FMB) provides a design

target for meeting all planned processor frequency requirements.

PCH

Platform Controller Hub. The chipset with centralized platform capabilities including

the main I/O interfaces along with display connectivity, audio features, power

management, manageability, security, and storage features.

PECI

The Platform Environment Control Interface (PECI) is a one-wire interface that

provides a communication channel between Intel processor and chipset components

to external monitoring devices.

Ψ

 ca

Case-to-ambient thermal characterization parameter (psi). A measure of thermal

solution performance using total package power. Defined as (T

CASE

 - T

LA

 ) / Total

Package Power. The heat source should always be specified for Y measurements.

PEG

PCI Express* Graphics. External Graphics using PCI Express* Architecture. It is a

high-speed serial interface where configuration is software compatible with the

existing PCI specifications.

PL1, PL2

Power Limit 1 and Power Limit 2

PPD

Pre-charge Power-down

Processor

The 64-bit multi-core component (package)

Processor Core

The term “processor core” refers to Si die itself, which can contain multiple execution

cores. Each execution core has an instruction cache, data cache, and 256-KB L2

cache. All execution cores share the L3 cache.

Processor Graphics

Intel Processor Graphics

Rank

A unit of DRAM corresponding to four to eight devices in parallel, ignoring ECC.

SCI

System Control Interrupt. SCI is used in the ACPI protocol.

SF

Strips and Fans

SMM

System Management Mode

SMX

Safer Mode Extensions

Storage Conditions

A non-operational state. The processor may be installed in a platform, in a tray, or

loose. Processors may be sealed in packaging or exposed to free air. Under these

conditions, processor landings should not be connected to any supply voltages, have

any I/Os biased, or receive any clocks. Upon exposure to “free air” (that is, unsealed

packaging or a device removed from packaging material), the processor must be

handled in accordance with moisture sensitivity labeling (MSL) as indicated on the

packaging material.

SVID

Serial Voltage Identification

TAC

Thermal Averaging Constant

TAP

Test Access Point

T

CASE

The case temperature of the processor, measured at the geometric center of the top-

side of the TTV IHS.

TCC

Thermal Control Circuit

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

14

Order No.: 328907-001