Intel E3-1226 v3 CM8064601575206 User Manual

SA_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

bus.

I/O

DDR3/DDR3L

SA_ECC_CB[7:0]

ECC Data Lines: Data Lines for ECC Check Byte.

I/O

DDR3/DDR3L

SA_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address to the SDRAM.

O

DDR3/DDR3L

SA_CK[3:0]

SDRAM Differential Clock: These signals are Channel A

SDRAM Differential clock signal pairs. The crossing of the

positive edge of SA_CK and the negative edge of its complement

SA_CK# are used to sample the command and control signals on

the SDRAM.

O

DDR3/DDR3L

SA_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh during STR

O

DDR3L

SA_CS#[3:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There is

one Chip Select for each SDRAM rank.

O

DDR3/DDR3L

SA_ODT[3:0]

On Die Termination: Active Termination Control.

O

DDR3/DDR3L

SB_BS[2:0]

Bank Select: These signals define which banks are selected

within each SDRAM rank.

O

DDR3/DDR3L

SB_WE#

Write Enable Control Signal: This signal is used with

SB_RAS# and SB_CAS# (along with SB_CS#) to define the

SDRAM Commands.

O

DDR3/DDR3L

SB_RAS#

RAS Control Signal: This signal is used with SB_CAS# and

SB_WE# (along with SB_CS#) to define the SRAM Commands.

O

DDR3L

SB_CAS#

CAS Control Signal: This signal is used with SB_RAS# and

SB_WE# (along with SB_CS#) to define the SRAM Commands.

O

DDR3/DDR3L

SB_DQS[8:0]

SB_DQSN[8:0]

Data Strobes: SB_DQS[8:0] and its complement signal group

make up a differential strobe pair. The data is captured at the

crossing point of SB_DQS[8:0] and its SB_DQS#[8:0] during

read and write transactions.

I/O

DDR3/DDR3L

SB_DQ[63:0]

Data Bus: Channel B data signal interface to the SDRAM data

bus.

I/O

DDR3/DDR3L

SB_ECC_CB[7:0]

ECC Data Lines: Data Lines for ECC Check Byte.

I/O

DDR3/DDR3L

SB_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address to the SDRAM.

O

DDR3/DDR3L

SB_CK[3:0]

SDRAM Differential Clock: Channel B SDRAM Differential

clock signal pair. The crossing of the positive edge of SB_CK

and the negative edge of its complement SB_CK# are used to

sample the command and control signals on the SDRAM.

O

DDR3/DDR3L

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

78

Order No.: 328907-001