Intel E5-2680 v3 CM8064401439612 User Manual

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

161

Datasheet Volume One

DDR3

DDR3 buffers: 1.5 V and 1.35 V tolerant

DMI2

Direct Media Interface Gen 2 signals. These signals are compatible with PCI Express* 

2.0 and 1.0 Signaling Environment AC Specifications.

Intel QPI

Current-mode 6.4 GT/s and 8.0 GT/s forwarded-clock Intel QuickPath Interconnect 

signaling

Open Drain CMOS

Open Drain CMOS (ODCMOS) buffers: 1.05 V tolerant

PCI Express*

PCI Express* interface signals. These signals are compatible with PCI Express* 3.0 

Signalling Environment AC Specifications and are AC coupled. The buffers are not 

3.3-V tolerant. Refer to the PCIe* specification.

Reference

Voltage reference signal.

SSTL

Source Series Terminated Logic (JEDEC SSTL_15)

Notes:
1.

Qualifier for a buffer type.

Differential

SSTL Output

DDR{0/1/2/3}_CLK_D[N/P][3:0]

Single ended

SSTL Output

DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N

CMOS1.5v Output

DDR_RESET_C{01/23}_N

Single ended

CMOS1.5v Output

DDR{0/1/2/3}_CS_N[9:0]
DDR{0/1/2/3}_ODT[5:0]
DDR{0/1/2/3}_CKE[5:0]

Reference Output

DDR_VREFDQTX_C{01/23}

Reference Input

DDR_VREFDQRX_C{01/23}
DDR{01/23}_RCOMP[2:0] 

Differential

SSTL Input/Output

DDR{0/1/2/3}_DQS_D[N/P][17:00]

Single ended

SSTL Input/Output

DDR{0/1/2/3}_DQ[63:00]
DDR{0/1/2/3}_ECC[7:0]

SSTL Input

DDR{0/1/2/3}_PAR_ERR_N

Single ended

CMOS1.5v Input

DRAM_PWR_OK_C{01/23}