Intel E5-2690 v3 CM8064401439416 User Manual

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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

Datasheet Volume One

The processor periodically samples temperature from the DIMM TSoD devices over a 
programmable interval and interpolates gaps or the BMC/Intel ME samples a 

motherboard thermal sensor in the memory subsection and provides this data to the 
PCU via the PECI interface. This data is combined with an energy based estimations 

calculated by the PCU. When needed, system memory is then throttled using CAS 

bandwidth control. The processor supports dynamic reprogramming of the memory 
thermal limits based on system thermal state by the BMC or Intel ME.

The processor includes a pair of new bi-directional memory thermal status signals 
useful for manageability schemes. Each signal presents and receives thermal status for 

a pair of memory channels (channels 0 and 1 and channels 2 and 3). 

• Input Function: The processor can periodically sense the MEM_HOT_{C01/C23}_N 

signals to detect if the platform is requesting a memory throttling event. 

Manageability hardware could drive this signal due to a memory voltage regulator 
thermal or electrical issue or because of a detected system thermal event (for 

example, fan is going to fail) other system devices are exceeding their thermal 

target. The input sense period of these signals are programmable, 100 us is the 
default value. The input sense assertion time recognized by the processor is 

programmable, 1 us is the default value. If the sense assertion time is programmed 

to zero, then the processor ignores all external assertions of MEM_HOT_{C01/
C23}_N signals (in effect they become outputs). 

• Output Function: The output behavior of the MEM_HOT_{C01/C23}_N signals 

supports Level mode. In this mode, MEM_HOT_{C01/C23}_N event temperatures 

are programmable via TEMP_OEM_HI, TEMP_LOW, TEMP_MID, and TEMP_HI 

threshold settings in the iMC. In Level mode, when asserted, the signal indicates to 
the platform that a BIOS-configured thermal threshold has been reached by one or 

more DIMMs in the covered channel pair.

The processor includes two integrated SMBus master controllers running at 100 KHz for 

dedicated PCU access to the serial presence detect (SPD) devices and thermal sensors 

(TSoD) on the DIMMs. Each controller is responsible for a pair of memory channels and 
supports up to eight SMBus slave devices. Note that clock-low stretching is not 

supported by the processor. To avoid design complexity and minimize package C-state 

transitions, the SMBus interface between the processor and DIMMs must be connected.

 

The SMBus controllers for the system memory interface support the following SMBus 

protocols/commands:

• Random byte Read
• Byte  Write
• I

2

C* Write to Pointer Register

• I

2

C Present Pointer Register Word Read

• I

2

C Pointer Write Register Read.

Refer to the System Management Bus (SMBus) Specification, Revision 2.0 for standing 

timing protocols and specific command structure details.