Intel Celeron M 530 1.73 GHz BX80537530 Data Sheet

57

COMP[3:0]

Analog

COMP[3:0] must be terminated on the system board using precision (1% 
tolerance) resistors. Refer to the platform design guides for more details on 
implementation.

D[63:0]#

Input/
Output

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path 
between the FSB agents, and must connect the appropriate pins on both agents. 
The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in a 
common clock period. D[63:0]# are latched off the falling edge of both 
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a 
pair of one DSTBP# and one DSTBN#. The following table shows the grouping 
of data signals to data strobes and DINV#.

Furthermore, the DINV# pins determine the polarity of the data signals. Each 
group of 16 data signals corresponds to one DINV# signal. When the DINV# 
signal is active, the corresponding data group is inverted and therefore sampled 
active high. 

DBR#

Output

DBR# (Data Bus Reset) is used only in processor systems where no debug port 
is implemented on the system board. DBR# is used by a debug port interposer 
so that an in-target probe can drive system reset. If a debug port is implemented 
in the system, DBR# is a no connect. DBR# is not a processor signal.

DBSY#

Input/
Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on 
the FSB to indicate that the data bus is in use. The data bus is released after 
DBSY# is deasserted. This signal must connect the appropriate pins on both 
FSB agents.

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction cannot be 
guaranteed in-order completion. Assertion of DEFER# is normally the 
responsibility of the addressed memory or Input/Output agent. This signal must 
connect the appropriate pins of both FSB agents.

DINV[3:0]#

Input/
Output

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the 
polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the 
data on the data bus is inverted. The bus agent will invert the data bus signals if 
more than half the bits, within the covered group, would change level in the next 
cycle.

D[15:0]#

0

0

D[31:16]#

1

1

D[47:32]#

2

2

D[63:48]#

3

3

DINV[3]#

D[63:48]#

DINV[2]#

D[47:32]#

DINV[1]#

D[31:16]#

DINV[0]#

D[15:0]#