Intel Celeron M 530 1.73 GHz BX80537530 Data Sheet

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The new packed, double-precision, floating-point instructions enhance performance for 
applications that require greater range and precision, including scientific and engineering 

applications and advanced 3D geometry techniques, such as ray tracing.

The processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The 400-MHz 

FSB uses source-synchronous transfer (SST) of address and data to improve performance by 
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X 

data bus, the address bus can deliver addresses two times per bus clock and is referred to as a 

“double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus 
provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning 

Transceiver Logic (AGTL+) signal technology, a variant of GTL+ signalling technology with low 

power enhancements.

Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel 

products.

#

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active 
state when driven to a low level. For example, when RESET# is low, a reset has been requested. 
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where 
the name does not imply an active state but describes part of a binary sequence (such as address 
or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a 
hex “A”, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). 

FSB

Front Side Bus refers to the interface between the processor and system core logic (also known as 

the chipset components).