Intel Quad-core Intel Xeon DP L5320 Passive BX80563L5320P Data Sheet

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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Regardless of whether or not TM1 or TM2 is enabled, in the event of a catastrophic 
cooling failure, the processor will automatically shut down when the silicon has reached 
an elevated temperature (refer to the THERMTRIP# definition in 

). At this 

point, the FSB signal THERMTRIP# will go active and stay active as described in 

. THERMTRIP# activation is independent of processor activity and does not 

generate any bus cycles. Intel also recommends the removal of V

TT

.

PECI offers an interface for thermal monitoring of Intel processor and chipset 
components. It uses a single wire, thus alleviating routing congestion issues. 

 shows an example of the PECI topology in a system with Quad-Core Intel® 

Xeon® Processor 5300 Series. PECI uses CRC checking on the host side to ensure 
reliable transfers between the host and client devices. Also, data transfer speeds across 
the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI 
interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and 
must be enabled through BIOS. More information on this can be found in the Conroe 
and Woodcrest Processor Family BIOS Writer’s Guide.

Fan speed control solutions based on PECI utilize a T

CONTROL

 value stored in the 

processor IA32_TEMPERATURE_TARGET MSR. This MSR uses the same offset 
temperature format as PECI, though it contains no sign bit. Thermal management 
devices should infer the T

CONTROL

 value as negative. Thermal management algorithms 

should utilize the relative temperature value delivered over PECI in conjunction with the 
MSR value to control or optimize fan speeds. 

 shows a conceptual fan control 

diagram using PECI temperatures.