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Intel Xeon 5120 1.86 GHz 124724 Data Sheet

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124724
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Dual-Core Intel
® 
Xeon
® 
Processor 5100 Series Datasheet
33
Electrical Specifications
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE 
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage 
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and 
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and 
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR 
implementation. Please refer to the appropriate platform design guide for details on VR implementation.
Figure 2-5. Dual-Core Intel® Xeon® Processor 5100 Series V
CC
 Static and Transient 
Tolerance Load Line
Notes:
1.
The V
CC_MIN
 and V
CC_MAX
 loadlines represent static and transient limits. Please see 
 for VCC 
overshoot specifications.
2.
Refer to 
 for processor VID information.
3.
Refer to 
CC
Static and Transient Tolerance
4.
The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE 
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage 
regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and 
VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and 
Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR 
implementation. Please refer to the appropriate platform design guide for details on VR implementations.
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
0
10
20
30
40
50
60
70
80
90
Icc [A]
V
cc [
V
]
Vcc
Maximum
Vcc
Minimum
Vcc
Typical
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
0
10
20
30
40
50
60
70
80
90
Icc [A]
V
cc [
V
]
Vcc
Maximum
Vcc
Minimum
Vcc
Typical