Hynix HMT351U6BFR8C-H9N0 User Manual

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DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066

 

as specified in the table 

below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “DDR3 Device 

Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation”

 

depending on Vih/Vil AC lev-

els.

Notes:
1. Vref = VrefDQ (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 30.
3. The ac peak noise on V

Ref

 may not allow V

Ref

 to deviate from V

RefDQ(DC)

 by more than +/-1% VDD (for 

reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.

VIH.CA(DC100)

DC input logic high

Vref + 0.100

VDD

Vref + 0.100

VDD

V

1

VIL.CA(DC100)

DC input logic low

VSS

Vref - 0.100

VSS

Vref - 0.100

V

1

VIH.CA(AC175)

AC input logic high

Vref + 0.175

Note2

-

-

V

1, 2

VIL.CA(AC175)

AC input logic low

Note2

Vref - 0.175

-

-

V

1, 2

VIH.CA(AC150)

AC Input logic high

Vref + 0.150

Note2

Vref + 0.150

Note2

V

1, 2

VIL.CA(AC150)

AC input logic low

Note2

Vref - 0.150

Note2

Vref - 0.150

V

1, 2

V

RefDQ(DC

)

Reference Voltage for DQ, 

DM inputs

0.49 * VDD

0.51 * VDD

0.49 * VDD

0.51 * VDD

V

3, 4

B48614/178.104.2.80/2010-10-18 17:07