Hynix HMT42GR7BFR4C-RDT8 User Manual
Rev. 1.0 / May. 2014
12
Functional Block Diagram
4GB, 512Mx72 Module(1Rank of x8)
CB[7:0]
DQS8
DQS8
DM8/DQS17
DQS17
DQS8
DM8/DQS17
DQS17
RRAS
A
RCA
SA
RS0A
RWEA
PCK0
A
PCK0A
RCKE0A
ROD
T0A
A[
N:
O]
A
Vtt
DQ[31:24]
DQS3
DQS3
DM3/DQS12
DQS12
DQS3
DM3/DQS12
DQS12
DQ[23:16]
DQS2
DQS2
DM2/DQS11
DQS11
DQS2
DM2/DQS11
DQS11
DQ[15:8]
DQS1
DQS1
DM1/DQS10
DQS10
DQS1
DM1/DQS10
DQS10
DQ[7:0]
DQS0
DQS0
DM0/DQS9
DQS9
DQS0
DM0/DQS9
DQS9
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D8
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
OD
T
A[
N:
O
]/B
A[
N:
O]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D3
DQ [7:0]
ZQ
RA
S
CA
S
CS
WE
CK
CK
CK
E
OD
T
A[
O
:N
]/BA[
N:
O]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D2
DQ [7:0]
ZQ
RA
S
CA
S
CS
WE
CK
CK
CK
E
OD
T
A[
O
:N]/BA[N
:O
]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D1
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
OD
T
A[
N:
O]
/B
A[
N
:O]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D0
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
OD
T
A[N
:O
]/B
A[N
:O]
DQ[39:32]
DQS4
DQS4
DM4/DQS13
DQS13
DQS4
DM4/DQS13
DQS13
RRASB
RCA
SB
RS0B
RWEB
PCK0
B
PCK0B
RCKE0B
ROD
T0B
A[
N:
O]
B
Vtt
DQ[47:40]
DQS5
DQS5
DM5/DQS14
DQS14
DQS5
DM5/DQS14
DQS14
DQ[55:48]
DQS6
DQS6
DM6/DQS15
DQS15
DQS6
DM6/DQS15
DQS15
DQ[63:56]
DQS7
DQS7
DM7/DQS16
DQS16
DQS7
DM7/DQS16
DQS16
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D4
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
OD
T
A[
O:
N
]/B
A[
O:
N]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D5
DQ [7:0]
ZQ
RA
S
CA
S
CS
WE
CK
CK
CK
E
OD
T
A[
O:
N]/B
A[
N
:O]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D6
DQ [7:0]
ZQ
RA
S
CA
S
CS
WE
CK
CK
CK
E
OD
T
A[O:N
]/
BA[N:O]
DQS
DQS
TDQS
TDQS
DQS
TDQS
TDQS
D7
DQ [7:0]
ZQ
RA
S
CA
S
CS
WE
CK
CK
CK
E
OD
T
A[
N
:O
]/BA[
N:
O
]
/B
A[
N:
O]
A
/B
A[
N:
O]
B
S0
S1
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A → CS0: SDRAMs D[3:0], D8
RS0B → CS0: SDRAMs D[7:4]
RS0B → CS0: SDRAMs D[7:4]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8
RRASA → RAS: SDRAMs D[7:4]
RBA[N:0]A → BA[N:0]: SDRAMs D[7:4]
RA[N:0]A → A[N:0]: SDRAMs D[7:4]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8
RRASA → RAS: SDRAMs D[3:0], D8
RCASA → CAS: SDRAMs D[7:4]
RCASA → CAS: SDRAMs D[3:0], D8
RWEA → WE: SDRAMs D[7:4]
RWEA → WE: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
RCKE0A → CKE0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
RODT0A → ODT0: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK0A → CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET
RST
RST: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330 Ω resistor to ground
1:
2
R
R
E
G
I
S
T
T
E
R
/
P
D0–D8
V
DD
V
TT
V
DDSPD
D0–D8
VREFDQ
SPD
VREFCA
V
SS
D0–D8
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240
Ω ±
1%.For all other resistor values refer to the
appropriate wiring diagram.
VDDSPD
EVENT
SCL
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
Integrated
TS
SA1
SA2
VSS
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local SK hynix sales representative
120 Ω
±1%
±1%
CK0
CK0
CK0
120 Ω
±1%
±1%
L
L
L