Hynix HMT42GR7BFR4C-RDT8 User Manual

Page of 71
Rev. 1.0 / May. 2014
31 
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL 
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level 
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU 
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 40.
note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling 
input differential signal shall become equal to or less than VIL(ac) level.
Differential AC and DC Input Levels
Symbol
Parameter
DDR3-800, 1066, 1333, 1600
Unit Notes
Min
Max
VIHdiff
Differential input high
+ 0.180
Note 3
V
1
VILdiff
Differential input logic low
Note 3
- 0.180
V
1
VIHdiff (ac)
Differential input high ac
2 x (VIH (ac) - Vref)
Note 3
V
2
VILdiff (ac)
Differential input low ac
Note 3
2 x (VIL (ac) - Vref)
V
2
Allowed time before ringback 
(tDVAC) for CK - CK and DQS - DQS
Slew 
Rate 
[V/ns]
DDR3-800/1066/1333/1600
DDR3-1866
tDVAC [ps]
@ VIH/Ldiff (ac)
 = 350mV
tDVAC [ps]
@ VIH/Ldiff (ac)
= 300mV
tDVAC [ps]
@ VIH/Ldiff (ac)
 = 270mV
(DQS-DQS)only 
(Optional)
tDVAC [ps]
@ VIH/Ldiff (ac)| 
= 300mV
tDVAC [ps]
@ VIH/Ldiff (ac)| 
= (CK-CK)only
min
max
min
max
min
max
min
max
min
max
> 4.0
75
-
175
-
214
-
134
-
139
-
4.0
57
-
170
-
214
-
134
-
139
-
3.0
50
-
167
-
191
-
112
-
118
-
2.0
38
-
119
146
67
77
1.8
34
-
102
-
131
-
52
-
63
-
1.6
29
-
81
-
113
-
33
-
45
-
1.4
22
-
54
-
88
-
9
-
23
-
1.2
13
-
19
-
56
-
note
-
note
-
1.0
0
-
note
-
11
-
note
-
note
-
< 1.0
0
-
note
-
note
-
note
-
note
-