DELL 2 x Intel Xeon E7-4860 338-BFMX User Manual

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Datasheet Volume 2 of 2 

characteristics like power consumed/saved, entry latency, exit latency. Memory 
contents may be retained or lost by a power state. A power state may be controlled by 
hardware or software or hybrid. A memory power node can be placed at various power 
states depending on the power savings versus latency trade off. the above power state 
characteristics are vital for OS/VMM to make this trade off. These numbers are also 
provided to OS by BIOS via the ACPI MPST Table.

Several new memory power states have been added into the EX server segment:

–Dynamic CKE (hardware assisted)
–Memory Standby (software assisted)
–Memory Offline (software assisted)

All the south-bound and north-bound lanes on the Intel SMI are placed in Disable_A 
state:

• The clocks driving the Intel 7500 Scalable Memory Buffer Interface are disabled.
• One processor socket memory controller will be in Standby and the other memory 

controller will continue to be active. All the DRAM devices behind the Intel 7500 
Scalable Memory Buffer are placed in self refresh.

• Intel 7500 Scalable Memory Buffer continues to be powered on and drives DRAM 

interface signals to support DIMMs in Self refresh When resuming from Standby to 
active state BIOS flow will be used to bring up the link.

• The same exit flow of self refresh will be used to bring DRAMs into active state.

The memory riser can be turned off (offline) and brought back on (online) via MPST 
commands, as specified in the ACPI MPST specification.