DELL 2 x Intel Xeon E7-4860 338-BFMX User Manual

Datasheet Volume 2 of 2

9

• Execute Disable Bit capability
• Direct-attach firmware to processor socket via serial flash interface

— Supports commodity 1-, 4-, 8-MB SPI Flash ROM devices 

This section defines the abbreviations, terminology, and other conventions used 
throughout this document.

 

<sz>

Region Size in System Address Map

RMW

Read Modify Write 

SIPI

Start IPI

IPI

Interprocessor Interrupt

Intel 7500 Scalable 

Memory Buffer

Advanced Memory Buffer

APIC

Advanced Programmable Interrupt Controller

BBox

Home Agent or Global Coherence Engine

Intel

®

 IBIST

Intel

®

 Interconnect Built-In Self Test

BMC

Baseboard Management Controller

BSP/SBSP

(System) Boot Strap Processor: A processor responsible for system initialization.

Clump

A collection of processors

CMP

Chip Multi-Processing

COH

Coherent 

Core(s)

A Processing Unit

Core/System Interface/

SPIS

Interface Logic block present in processor, for interfacing the processor core 

clusters with Uncore block. 

CRC

Cyclic Redundancy Code

DC-SFROM

Direct Connect Serial Flash ROM

DDR

Double Data Rate

DIMM

Dual In Line Memory Module. A packaging arrangement of memory devices on a 

socketable substrate.

ECC

Error Correction Code

EOI

End of Interrupt 

FBD

Fully Buffered DIMM

FLIT

Smallest unit of flow control for the Link layer.

FW

Firmware

HAR

Hot Add/Remove 

IMC

Integrated Memory Controller

Intel

®

 QPI

Intel

® 

QuickPath Interconnect. A Cache Coherent, Link-based interconnect 

specification for Intel processor, chipset, and IO bridge components.

Intel

®

 SMI 

Intel

®

 Scalable Memory Interconnect (formerly “FBD2” or “Fully Buffered DIMM 

2 interface”)