Intel PentiumD 950 HH80553PG0964M User Manual

22

I

ENHANCED_

AUTO_HALT

Processor number

Extreme Edition 965
Extreme Edition 955

960
950
940

I

CC

 Enhanced Auto Halt for 

775_VR_CONFIG_05B 
(Performance)

3.73 GHz
3.46 GHz
3.60 GHz
3.40 GHz
3.20 GHz

—

—

68
68
60
60
60

A

Processor number

960

950/945
940/935
930/925
920/915

I

CC

 Enhanced Auto Halt for 

775_VR_CONFIG_05A 
(Mainstream)

3.60 GHz
3.40 GHz
3.20 GHz
3.00 GHz
2.80 GHz

—

—

48
48
48
48
48

I

TCC

I

CC

 TCC active

—

—

I

CC

A

12

V

TT

FSB termination voltage 
(DC + AC specifications)

1.14

1.20

1.26

V

13, 14

VTT_OUT_
LEFT and 
VTT_OUT_
RIGHT I

CC

DC Current that may be drawn from VTT_OUT_LEFT and 
VTT_OUT_RIGHT per pin

—

—

580

mA

I

TT

Steady-state FSB termination current

—

—

4.5

A

15, 16

I

TT_P

OWER

-

UP

Power-up FSB termination current

—

—

7.5

A

I

CC_VCCA

I

CC

 for PLL lands

—

—

70

mA

I

CC_VCCIOPLL

I

CC

 for I/O PLL land

—

—

52

mA

I

CC_GTLREF

I

CC

 for GTLREF

—

—

200

μA

1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These

specifications will be updated with characterized data from silicon measurements at a later date.

2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can

not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same

frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during

a power management event (Enhanced Intel SpeedStep technology or Enhanced HALT State). 

4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required.

See 

 and 

 for more information.

5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz

bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire

on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.

6. Refer to 

 for the minimum, typical, and maximum V

CC

 allowed for a given current. The processor should not

be subjected to any V

CC

 and I

CC

 combination wherein V

CC

 exceeds V

CC_MAX

 for a given current.

7.

I

CC_MAX

 specification is based on V

CC

 Maximum loadline. Refer to 

 for details. 

8. I

CC_RESET

 is specified while RESET# is active. 

9. The current specified is also for AutoHALT State.

10.I

SGNT

 and I

CC_ENHANCED_AUTO_HALT

 are specified at V

CC_TYP

 and T

C

 = 50 °C.

11.These parameters are based on design characterization and are not tested.

12.The maximum instantaneous current the processor will draw while the thermal control circuit is active (as indicated by the

assertion of PROCHOT#) is the same as the maximum I

CC

 for the processor.

13.V

TT

 must be provided via a separate voltage source and not be connected to V

CC

. This specification is measured at the land.

14.Baseboard bandwidth is limited to 20 MHz.