Intel PentiumD 950 HH80553PG0964M User Manual
Product codes
HH80553PG0964M
Datasheet
29
Electrical Specifications
.
Table 11.
GTL+ Asynchronous Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
V
TT
/2 – (0.10 * V
TT
)
V
2, 3
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals V
IH
= GTLREF + (0.10 * V
TT
) and
V
IL
= GTLREF – (0.10 * V
TT
).
V
IH
Input High Voltage
V
TT
/2 + (0.10 * V
TT
)
V
TT
V
4, 5, 6,
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the signal quality
specifications.
6. The V
TT
referred to in these specifications refers to instantaneous V
TT
.
V
OH
Output High Voltage
0.90*V
TT
V
TT
V
7,
,
7. All outputs are open drain.
I
OL
Output Low Current
—
V
TT
/
[(0.50*R
TT_MIN
)+(R
ON_MIN
)]
A
8
8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
I
LI
Input Leakage Current
N/A
± 200
µA
9
9. Leakage to V
SS
with land held at V
TT
.
I
LO
Output Leakage
Current
Current
N/A
± 200
µA
10
10.Leakage to V
TT
with land held at 300 mV.
R
ON
Buffer On Resistance
6
12
W
Table 12.
TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes
1, 2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
V
HYS
Input Hysteresis
120
396
mV
3, 4
3. Leakage to V
TT
with land held at 300 mV.
4.
V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
, for all TAP inputs.
V
T+
PWRGOOD Input low-
to-high threshold
voltage
to-high threshold
voltage
0.5 * (V
TT +
V
HYS_MIN
+ 0.24)
0.5 * (V
TT +
V
HYS_MAX
+ 0.24)
V
5, 6
5. The V
TT
referred to in these specifications refers to instantaneous V
TT
.
6. 0.24 V is defined at 20% of nominal V
TT
of 1.2 V.
TAP Input low-to-high
threshold voltage
threshold voltage
0.5 * (V
TT +
V
HYS_MIN
)
0.5 * (V
TT +
V
HYS_MAX
)
V
V
T-
PWRGOOD Input high-
to-low threshold voltage
to-low threshold voltage
0.4 * V
TT
0.6 * V
TT
V
TAP Input high-to-low
threshold voltage
threshold voltage
0.5 * (V
TT
– V
HYS_MAX
) 0.5 * (V
TT
– V
HYS_MIN
)
V
V
OH
Output High Voltage
N/A
V
TT
V
I
OL
Output Low Current
—
22.2
mA
7
7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
I
LI
Input Leakage Current
—
± 200
µA
8
8. Leakage to Vss with land held at V
TT
.
I
LO
Output Leakage Current
—
± 200
µA
R
ON
Buffer On Resistance
6
12
W