Intel PentiumD 950 HH80553PG0964M User Manual
Product codes
HH80553PG0964M
Electrical Specifications
32
Datasheet
2.7
Clock Specifications
2.7.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to
for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
2.7.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Pentium D processor 900 sequence operates at 800 MHz FSB frequency (selected
by a 200 MHz BCLK[1:0] frequency). The Pentium processor Extreme Edition 955, 965
operate at 1066 MHz FSB frequency (selected by a 266 MHz BCLK[1:0] frequency).
Table 17.
Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core Frequency to
FSB Frequency
Core Frequency
(200 MHz BCLK/
800 MHz FSB)
Core Frequency
(266 MHz BCLK/
1066 MHz FSB)
Notes
1, 2
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
1/12
2.40 GHz
3.20 GHz
-
1/13
2.60 GHz
3.46 GHz
-
1/14
2.80 GHz
3.73 GHz
-
1/15
3 GHz
4 GHz
-
1/16
3.20 GHz
4.26 GHz
-
1/17
3.40 GHz
4.53 GHz
-
1/18
3.60 GHz
4.80 GHz
-
1/19
3.80 GHz
5.06 GHz
-
1/20
4 GHz
RESERVED
-
1/21
4.20 GHz
RESERVED
-
1/22
4.40 GHz
RESERVED
-
1/23
4.60 GHz
RESERVED
-
1/24
4.80 GHz
RESERVED
-
1/25
5 GHz
RESERVED
-