Intel X3460 BV80605001908AL User Manual

Product codes
BV80605001908AL
Page of 98
Power Management
44
Datasheet, Volume 1
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM 
interface. There are four SDRAM operations associated with the Clock Enable (CKE) 
signals, which the SDRAM controller supports. The processor drives four CKE pins to 
perform these operations.
4.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized 
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the 
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a 
configuration register. Using this method, CKE is ensured to remain inactive for much 
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices 
are stable.
4.3.2.2
Conditional Self-Refresh
The processor conditionally places memory into self-refresh in the C3 and C6 low power 
states. 
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending 
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals 
remain LOW so the SDRAM devices perform self refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as 
there are no memory requests to service. The target usage is shown in 
.
4.3.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle 
conditions, a given memory rank may be powered down. The IMC implements 
aggressive CKE control to dynamically put the DRAM devices in a power down state. 
The processor core controller can be configured to put the devices in active power down 
(CKE de-assertion with open pages) or precharge power down (CKE de-assertion with 
all pages closed). Precharge power down provides greater power savings but has a 
bigger performance impact, since all pages will first be closed before putting the 
devices in power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh 
cycle and all ranks are powered down at the end of refresh.
Table 4-6.
Targeted Memory State Conditions
Mode
Memory State with External Graphics
C0, C1, C1E
Dynamic memory rank power down based on idle conditions.
C3, C6
Dynamic memory rank power down based on idle conditions 
If there are no memory requests, then enter self-refresh. Otherwise, use dynamic memory 
rank power down based on idle conditions.
S4
Memory power down (contents lost)