Intel S1400SP4 DBS1400SP4 User Manual
Product codes
DBS1400SP4
Intel® Server Board S1400SP TPS
Server Board Power Distribution
Revision 1.0
Intel order number G64248-001
105
The measurement shall be made across a 100Ω resistor between each of DC outputs, including
ground at the DC power connector and chassis ground (power subsystem enclosure).
The test set-up shall use a FET probe such as Tektronix* model P6046 or equivalent.
ground at the DC power connector and chassis ground (power subsystem enclosure).
The test set-up shall use a FET probe such as Tektronix* model P6046 or equivalent.
12.2.10 Soft Starting
The Power Supply shall contain control circuit which provides monotonic soft start for its outputs
without overstress of the AC line or any power supply components at any specified AC line or
load conditions.
without overstress of the AC line or any power supply components at any specified AC line or
load conditions.
12.2.11 Zero Load Stability Requirements
When the power subsystem operates in a no load condition, it does not need to meet the output
regulation specification, but it must operate without any tripping of over-voltage or other fault
circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and
source current without fault.
regulation specification, but it must operate without any tripping of over-voltage or other fault
circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and
source current without fault.
12.2.12 Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined below. This is
measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A 10
measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A 10
µF
tantalum capacitor in parallel with a 0.1
µF ceramic capacitor is placed at the point of
measurement.
Table 58. Ripples and Noise
+12V
+5VSB
120mVp-p
50mVp-p
12.2.13 Timing Requirements
These are the timing requirements for the power supply operation. The output voltages must
rise from 10% to within regulation limits (T
rise from 10% to within regulation limits (T
vout_rise
) within 2 to 50ms, except for 5VSB - it is
allowed to rise from 1 to 25ms. The +12V , output voltage should start to rise approximately at
the same time. All outputs must rise monotonically. Each output voltage shall reach regulation
within 50ms (T
the same time. All outputs must rise monotonically. Each output voltage shall reach regulation
within 50ms (T
vout_on
) of each other during turn on of the power supply. Each output voltage shall
fall out of regulation within 400ms (T
vout_off
) of each other during turn off. Table below shows the
timing requirements for the power supply being turned on and off from the AC input, with PSON
held low and the PSON signal, with the AC input applied. All timing requirements must be met
for the cross loading condition.
held low and the PSON signal, with the AC input applied. All timing requirements must be met
for the cross loading condition.
Table 59. Output Voltage Timing
Item
Description
MIN
MAX
UNITS
T
vout_rise
Output voltage rise time from each main output.
2
50
ms
Output rise time for the 5Vstby output.
1
25
ms
T
vout_on
All main outputs must be within regulation of each other within this time.
50
ms
T
vout_off
All main outputs must leave regulation within this time.
400
ms