Intel S1400SP4 DBS1400SP4 User Manual
Product codes
DBS1400SP4
Intel® Server Board S1400SP TPS
Functional Architecture
Revision 1.0
Intel order number G64248-001
23
When Mirroring Mode is operational, the system treats Correctable Errors the same way as it
would in Independent channel mode. There is a correctable error threshold. Correctable error
counts accumulate by rank, and the first event is logged.
What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data “in process”. Without Mirroring, the system would be expected to
“Blue Screen” and halt, possibly with serious impact to operations. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the “mirror image” channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO
Event, the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a
single non-redundant channel, but without impacting operations, and the Mirroring Fail Over
Event is logged to SEL to alert the user that there is memory hardware that has failed and
needs to be replaced.
In Mirrored Channel Mode, the memory contents are mirrored between Channel B and Channel
C. As a result of the mirroring, the total physical memory available to the system is half of what is
populated. Mirrored Channel Mode requires that Channel B and Channel C must be populated
identically with regards to size and organization. DIMM slot populations within a channel do not
have to be identical but the same DIMM slot location across Channel B and Channel C must be
populated the same.
would in Independent channel mode. There is a correctable error threshold. Correctable error
counts accumulate by rank, and the first event is logged.
What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data “in process”. Without Mirroring, the system would be expected to
“Blue Screen” and halt, possibly with serious impact to operations. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the “mirror image” channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO
Event, the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a
single non-redundant channel, but without impacting operations, and the Mirroring Fail Over
Event is logged to SEL to alert the user that there is memory hardware that has failed and
needs to be replaced.
In Mirrored Channel Mode, the memory contents are mirrored between Channel B and Channel
C. As a result of the mirroring, the total physical memory available to the system is half of what is
populated. Mirrored Channel Mode requires that Channel B and Channel C must be populated
identically with regards to size and organization. DIMM slot populations within a channel do not
have to be identical but the same DIMM slot location across Channel B and Channel C must be
populated the same.
3.2.2.4.4
Lockstep Channel Mode
In lockstep channel mode the cache-line is split across channels. This is done to support Single
Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the same
address is used on both channels, such that an address error on any channel is detectable by
bad ECC. The iMC module always accumulates 32-bytes before forwarding data so there is no
latency benefit for disabling ECC.
Lockstep channels must be populated identically. That is, each DIMM in one channel must have
a corresponding DIMM of identical organization (number ranks, number banks, number rows,
number columns). DIMMs may be of different speed grades, but the iMC module will be
configured to operate all DIMMs according to the slowest parameters present by the Memory
Reference Code (MRC).
Performance in lockstep mode cannot be as high as with independent channels. The burst
length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep
mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs on
independent channels are configured to deliver a burst length of eight. The maximum read
bandwidth for a given Rank is half of peak. There is another drawback in using lockstep mode,
that is, higher power consumption since the total activation power is about twice of the
independent channel operation if comparing to same type of DIMMs.
In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel B
and Channel C. Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices.
Lockstep Channel Mode requires that Channel B and Channel C must be populated identically
with regards to size and organization. DIMM slot populations within a channel do not have to be
identical but the same DIMM slot location across Channel B and Channel C must be populated
the same.
Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the same
address is used on both channels, such that an address error on any channel is detectable by
bad ECC. The iMC module always accumulates 32-bytes before forwarding data so there is no
latency benefit for disabling ECC.
Lockstep channels must be populated identically. That is, each DIMM in one channel must have
a corresponding DIMM of identical organization (number ranks, number banks, number rows,
number columns). DIMMs may be of different speed grades, but the iMC module will be
configured to operate all DIMMs according to the slowest parameters present by the Memory
Reference Code (MRC).
Performance in lockstep mode cannot be as high as with independent channels. The burst
length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep
mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs on
independent channels are configured to deliver a burst length of eight. The maximum read
bandwidth for a given Rank is half of peak. There is another drawback in using lockstep mode,
that is, higher power consumption since the total activation power is about twice of the
independent channel operation if comparing to same type of DIMMs.
In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel B
and Channel C. Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices.
Lockstep Channel Mode requires that Channel B and Channel C must be populated identically
with regards to size and organization. DIMM slot populations within a channel do not have to be
identical but the same DIMM slot location across Channel B and Channel C must be populated
the same.