Intel E3-1275L v3 CM8064601575224 User Manual

method to use on a dynamic basis. BIOS is not required to select a specific method

(as with previous-generation processors supporting TM1 or TM2). The temperature at

which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory

calibrated and is not user configurable. Snooping and interrupt processing are

performed in the normal manner while the TCC is active.

When the TCC activation temperature is reached, the processor will initiate TM2 in

attempt to reduce its temperature. If TM2 is unable to reduce the processor

temperature, TM1 will be also be activated. TM1 and TM2 will work together (clocks

will be modulated at the lowest frequency ratio) to reduce power dissipation and

temperature.

With a properly designed and characterized thermal solution, it is anticipated that the

TCC will only be activated for very short periods of time when running the most power

intensive applications. The processor performance impact due to these brief periods of

TCC activation is expected to be so minor that it would be immeasurable. An under-

designed thermal solution that is not able to prevent excessive activation of the TCC in

the anticipated ambient environment may cause a noticeable performance loss, and in

some cases may result in a T

CASE

 that exceeds the specified maximum temperature

and may affect the long-term reliability of the processor. In addition, a thermal

solution that is significantly under designed may not be capable of cooling the

processor even when the TCC is active continuously. See the appropriate processor

Thermal Mechanical Design Guidelines for information on designing a compliant

thermal solution.

The Thermal Monitor does not require any additional hardware, software drivers, or

interrupt handling routines. The following sections provide more details on the

different TCC mechanisms used by the processor.

When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures

reported using PECI may not equal zero when PROCHOT# is activated), the TCC will

be activated and the PROCHOT# signal will be asserted if configured as bi-directional.

This indicates the processor temperature has met or exceeded the factory calibrated

trip temperature and it will take action to reduce the temperature.

Upon activation of the TCC, the processor will stop the core clocks, reduce the core

ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this

frequency transition that occurs within 2 us. Once the clocks have been restarted at

the new lower frequency, processor activity resumes while the core voltage is reduced

by the internal voltage regulator. Running the processor at the lower frequency and

voltage will reduce power consumption and should allow the processor to cool off. If

after 1 ms the processor is still too hot (the temperature has not dropped below the

TCC activation point, DTS still = 0 and PROCHOT is still active), then a second

frequency and voltage transition will take place. This sequence of temperature

checking and frequency and voltage reduction will continue until either the minimum

frequency has been reached or the processor temperature has dropped below the TCC

activation point.

If the processor temperature remains above the TCC activation point even after the

minimum frequency has been reached, then clock modulation (described below) at

that minimum frequency will be initiated.

There is no end user software or hardware mechanism to initiate this automated TCC

activation behavior.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

70

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