Intel Quad-core Intel Xeon DP L5335 Active BX80563L5335A Data Sheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

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An on-die PLL filter solution is implemented on the processor. The 

V

CCPLL

 input is used 

to provide power to the on chip PLL of the processor. Please refer to 

 for DC 

specifications. Refer to the appropriate platform design guidelines for decoupling and 
routing guidelines.

The Voltage Identification (VID) specification for the processor is defined by the Voltage 
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design 
Guidelines. The voltage set by the VID signals is the reference VR output voltage to be 
delivered to the processor Vcc pins. Please refer to 

 for the DC specifications 

for these signals. A voltage range is provided in 

 and changes with 

frequency. The specifications have been set such that one voltage regulator can 
operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two 
devices at the same core frequency may have different default VID settings. This is 
reflected by the VID range values provided in 

The Quad-Core Intel® Xeon® Processor 5300 Series uses six voltage identification 
signals, VID[6:1], to support automatic selection of power supply voltages. 

 

specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table 
refers to a high voltage level and a ‘0’ refers to a low voltage level. The definition 
provided in 

 is not related in any way to previous Intel® Xeon® processors or 

voltage regulator designs. If the processor socket is empty (VID[6:1] = 111111), or 
the voltage regulation circuit cannot supply the voltage that is requested, the voltage 
regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise 
Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details.

Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down 
(EVRD) 11.0 Design Guidelines defines VID[7:0], VID[7] and VID[0] are not used on 
the Quad-Core Intel® Xeon® Processor 5300 Series. Please refer to the Quad-Core 
Intel® Xeon® Processor E5300 Series, Harpertown and Wolfdale-DP Processors 
Compatibility Design Guide for details.

The Quad-Core Intel® Xeon® Processor 5300 Series provide the ability to operate 
while transitioning to an adjacent VID and its associated processor core voltage (V

CC

). 

This will represent a DC shift in the load line. It should be noted that a low-to-high or 
high-to-low voltage state change may result in as many VID transitions as necessary to 
reach the target core voltage. Transitions above the specified VID are not permitted. 

 includes VID step sizes and DC shift ranges. Minimum and maximum 

voltages must be maintained as shown in 

.

The VRM or EVRD utilized must be capable of regulating its output to the value defined 
by the new VID. DC specifications for dynamic VID transitions are included in 

. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage 

Regulator-Down (EVRD) 11.0 Design Guidelines for further details.

Power source characteristics must be guaranteed to be stable whenever the supply to 
the voltage regulator is stable.