Intel Quad-core Intel Xeon DP L5335 Active BX80563L5335A Data Sheet

26

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

1.

Not all Quad-Core Intel® Xeon® Processor 5300 Series support the additional signals A[37:36]#. 

Processors that support these signals will be outlined in the Quad-Core Intel® Xeon® Processor 5300 

Series NDA Specification Update.

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize 
CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, 
and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain 
signals are required to be asserted/deasserted for at least eight BCLKs in order for the 
processor to recognize the proper signal state. See 

 for the DC 

specifications. See 

 for additional timing requirements for entering and 

leaving the low power states.

Due to the voltage levels supported by other components in the Test Access Port (TAP) 
logic, it is recommended that the processor(s) be first in the TAP chain and followed by 
any other components within the system. A translation buffer should be used to 
connect to the rest of the chain unless one of the other components is capable of 
accepting an input of the appropriate voltage. Similar considerations must be made for 
TCK, TDO, TMS, and TRST#. Two copies of each signal may be required with each 
driving a different voltage level. 

PECI is an Intel proprietary one-wire interface that provides a communication channel 
between Intel processor and external thermal monitoring devices. The Quad-Core 
Intel® Xeon® Processor 5300 Series contains Digital Thermal Sensors (DTS) 
distributed throughout the die. These sensors are implemented as analog-to-digital 
converters calibrated at the factor for reasonable accuracy to provide a digital 
representation of relative processor temperature. PECI provides an interface to relay 
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information may be found in the Platform Environment 
Control Interface (PECI) External Architecture Specification.

A PECI device interface operates at a nominal voltage set by V

TT

. The set of DC 

electrical specifications shown in 

 is used with devices normally operating 

from a V

TT

 interface supply. V

TT

 nominal levels will vary between processor families. All 

PECI devices will operate at the V

TT

 level determined by the processor installed in the 

system. For V

TT

 specifications, refer to 

.

V

in

Input Voltage Range

-0.150

V

TT

V

V

hysteresis

Hysteresis

0.1 * V

TT

N/A

V

V

N

Negative-edge threshold 

voltage

0.275 * V

TT

0.500 * V

TT

V