Intel Quad-core Intel Xeon DP X5335 Active BX80563X5335A Data Sheet

Product codes
BX80563X5335A
Page of 124
Electrical Specifications
20
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid processor core frequencies, refer to the Quad-Core Intel® Xeon® Processor 5300 Series 
Specification Update.
4.
The lowest bus ratio supported is 1/6.
2.4.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual 
processor. BSEL[2:0] are CMOS outputs which must be pulled up to V
TT
, and are used 
to select the FSB frequency. Please refer to 
defines the possible combinations of the signals and the frequency associated with each 
combination. The frequency is determined by the processor(s), chipset, and clock 
synthesizer. All FSB agents must operate at the same core and FSB frequency. See the 
appropriate platform design guidelines for further details.
Table 2-1.
Core Frequency to FSB Multiplier Configuration
Core Frequency 
to FSB 
Multiplier
Core Frequency with 
333
.333 MHz Bus 
Clock
Core Frequency with 
266.666 MHz Bus 
Clock
Notes
1/6
2 GHz
1.60 GHz
1, 2, 3, 4
1/7
2.33 GHz
1.86 GHz
1, 2, 3
1/8
2.66 GHz
2.13 GHz
1, 2, 3
1/9
3 GHz
2.40 GHz
1, 2, 3
1/10
3.33 GHz
2.66 GHz
1, 2, 3
1/11
3.66 GHz
2.93 GHz
1, 2, 3
1/12
4 GHz
3.20 GHz
1, 2, 3
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
BSEL1
BSEL0
Bus Clock Frequency
0
0
0
266.666 MHz
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
333.333 MHz
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved