Intel Quad-core Intel Xeon DP X5335 Active BX80563X5335A Data Sheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

85

1.

For this processor land on the Quad-Core Intel® Xeon® Processor 5300 Series, the maximum number of symmetric agents is 

one. Maximum number of priority agents is zero.

2.

For this processor land on the Quad-Core Intel® Xeon® Processor 5300 Series, the maximum number of symmetric agents is 

two. Maximum number of priority agents is zero.

3.

For this processor land on the Quad-Core Intel® Xeon® Processor 5300 Series, the maximum number of symmetric agents is 

two. Maximum number of priority agents is one. 

4.

Not all Quad-Core Intel® Xeon® Processor 5300 Series support signals A[37:36]#. Processors that support these signals will 

be outlined in the Quad-Core Intel® Xeon® Processor 5300 Series NDA Specification Update.

TESTIN1
TESTIN2

I
I

Connect the TESTIN1 and TESTIN2 signals together, then terminate the net with a 51 

Ω resistor to V

TT

.

THERMTRIP#

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction 

temperature has reached a temperature beyond which permanent silicon damage 

may occur. Measurement of the temperature is accomplished through an internal 

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal 

clocks (thus halting program execution) in an attempt to reduce the processor 

junction temperature. To protect the processor its core voltage (V

CC

) must be 

removed following the assertion of THERMTRIP#. Intel also recommends the removal 

of V

TT

 when THERMTRIP# is asserted.

Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of 

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, 

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion 

of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction 

temperature remains at or above the trip level, THERMTRIP# will again be asserted 

within 10 μs of the assertion of PWRGOOD.

1

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.

TRDY#

I

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a 

write or implicit writeback data transfer. TRDY# must connect the appropriate pins of 

all FSB agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low 

during power on Reset.

V

CCPLL

I

The Quad-Core Intel® Xeon® Processor 5300 Series implement an on-die PLL filter 

solution. The V

CCPLL

 input is used as a PLL supply voltage.

VCC_DIE_SENSE
VCC_DIE_SENSE2

O

VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated, low impedance 

connection to the processor core power and ground. This signal should be connected 

to the voltage regulator feedback signal, which insures the output voltage (that is, 

processor voltage) remains within specification. Please see the applicable platform 

design guide for implementation details.

VID[6:1]

O

VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply 

voltages (V

CC

). These are CMOS signals that are driven by the processor and must be 

pulled up through a resistor. Conversely, the voltage regulator output must be 

disabled prior to the voltage supply for these pins becomes invalid. The VID pins are 

needed to support processor voltage specification variations. See 

 for 

definitions of these pins. The VR must supply the voltage that is requested by these 

pins, or disable itself.

VID_SELECT

O

VID_SELECT is an output from the processor which selects the appropriate VID table 

for the Voltage Regulator. This signal is not connected to the processor die. This signal 

is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series package.

VSS_DIE_SENSE
VSS_DIE_SENSE2

O

VSS_DIE_SENSE and VSS_DIE_SENSE2 provides an isolated, low impedance 

connection to the processor core power and ground. This signal should be connected 

to the voltage regulator feedback signal, which insures the output voltage (that is, 

processor voltage) remains within specification. Please see the applicable platform 

design guide for implementation details.

VTT

P

The FSB termination voltage input pins. Refer to 

 for further details.

VTT_OUT

O

The VTT_OUT signals are included in order to provide a local V

TT

 for some signals that 

require termination to V

TT

 

on the motherboard.

VTT_SEL

O

The VTT_SEL signal is used to select the correct V

TT

 voltage level for the processor. 

VTT_SEL is a no-connect on the Quad-Core Intel® Xeon® Processor 5300 Series 

package.