Intel Quad-core Intel Xeon DP X5335 Passive BX80563X5335P Data Sheet

Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

41

1.

The V

CC_MIN

 and V

CC_MAX

 loadlines represent static and transient limits. Please see 

 for VCC 

overshoot specifications.

2.

Refer to 

 for processor VID information.

3.

Refer to 

CC

Static and Transient Tolerance.

4.

The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE 

lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Voltage regulation feedback for voltage 

regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and 

VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Refer to the Voltage Regulator Module (VRM) and 

Enterprise Voltage Regulator Down (EVRD) 11.0 Design Guidelines for socket load line guidelines and VR 

implementation. Please refer to the appropriate platform design guide for details on VR implementation.

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

V

IL

 is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low 

value.

3.

V

IH

 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 

value.

4.

V

IH

 and V

OH

 may experience excursions above V

TT

. However, input signal drivers must comply with the 

signal quality specifications.

5.

This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics. 

Measured at 0.31*V

TT

. R

ON

 (min) = 0.225*R

TT

. R

ON

 (typ) = 0.250*R

TT

. R

ON

 (max) = 0.275*R

TT

.

V

IL

Input Low Voltage

-0.10

0

GTLREF-0.10

V

2,4,6

V

IH

Input High Voltage

GTLREF+0.10

V

TT

V

TT

+0.10

V

3,6

V

OH

Output High Voltage

V

TT 

- 0.10

N/A

V

TT

V

4,6

R

ON

Buffer On Resistance

10.00

11.50

13.00

Ω

5

I

LI

Input Leakage Current

N/A

N/A

± 200

μA

7,8