IBM Intel Xeon X7350 44E4243 Data Sheet
Product codes
44E4243
Features
112
Document Number: 318080-002
processor. The chipset needs to account for a variable number of processors asserting
the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states.
the Stop Grant SBC on the bus before allowing the processor to be transitioned into one
of the lower processor power states.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
HALT or Extended HALT State
The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state
must be enabled for the processor to remain within its specifications. The
Extended HALT state requires support for dynamic VID transitions in the platform.
must be enabled for the processor to remain within its specifications. The
Extended HALT state requires support for dynamic VID transitions in the platform.
7.2.2.1
HALT State
HALT is a low power state entered when the processor has executed the HALT or
MWAIT instruction. When one of the processor cores executes the HALT or MWAIT
instruction, that processor core is halted; however, the other processor cores continue
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
MWAIT instruction. When one of the processor cores executes the HALT or MWAIT
instruction, that processor core is halted; however, the other processor cores continue
normal operation. The processor will transition to the Normal state upon the occurrence
of SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the
front side bus. RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT state. See the Intel®64 and IA-32 Architectures Software
Developer's Manual, Volume III: System Programming Guide for more information.
Normal Mode or the HALT state. See the Intel®64 and IA-32 Architectures Software
Developer's Manual, Volume III: System Programming Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT state. When
the system deasserts STPCLK#, the processor will return execution to the HALT state.
the system deasserts STPCLK#, the processor will return execution to the HALT state.
While in HALT state, the processor will process front side bus snoops and interrupts.
7.2.2.2
Extended HALT State
Extended HALT state is a low power state entered when all processor cores have
executed the HALT or MWAIT instructions and Extended HALT state has been enabled
via the BIOS. When one of the processor cores executes the HALT instruction, that
processor core is halted; however, the other processor cores continue normal
operation. The Extended HALT state is a lower power state than the HALT state or Stop
Grant state. The Extended HALT state must be enabled for the processor to remain
within its specifications.
executed the HALT or MWAIT instructions and Extended HALT state has been enabled
via the BIOS. When one of the processor cores executes the HALT instruction, that
processor core is halted; however, the other processor cores continue normal
operation. The Extended HALT state is a lower power state than the HALT state or Stop
Grant state. The Extended HALT state must be enabled for the processor to remain
within its specifications.
Note:
Not all Intel
®
Xeon
®
Processor 7200 Series and 7300 Series are capable of supporting
Extended HALT State. More detail on which processor frequencies will support this
feature will be provided in future releases of the Intel® Xeon® Processor 7200, 7300
Series Specification Update when available.
The processor will automatically transition to a lower core frequency and voltage
operating point before entering the Extended HALT state. Note that the processor FSB
frequency is not altered; only the internal core frequency is changed. When entering
the low power state, the processor will first switch to the lower bus to core frequency
ratio and then transition to the lower voltage (VID).
operating point before entering the Extended HALT state. Note that the processor FSB
frequency is not altered; only the internal core frequency is changed. When entering
the low power state, the processor will first switch to the lower bus to core frequency
ratio and then transition to the lower voltage (VID).
While in the Extended HALT state, the processor will process bus snoops.