IBM Intel Xeon X7350 44E4243 Data Sheet
Product codes
44E4243
Features
118
Document Number: 318080-002
Note:
1.
This addressing scheme will support up to 8 processors on a single SMBus.
7.4.2
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge
a Write Byte command but ignore the data. The Scratch EEPROM responds to Read
Byte and Write Byte commands.
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge
a Write Byte command but ignore the data. The Scratch EEPROM responds to Read
Byte and Write Byte commands.
diagrams the Read Byte command.
diagrams the Write Byte command. Following a write cycle to the scratch
ROM, software must allow a minimum of 10 ms before accessing either ROM of the
processor.
processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 7-3.
Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
1
Device Select
R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
A2h/A3h
1010
0
0
1
X
A4h/A5h
1010
0
1
0
X
A6h/A7h
1010
0
1
1
X
A8h/A9h
1010
1
0
0
X
AAh/ABh
1010
1
0
1
X
ACh/ADh
1010
1
1
0
X
AEh/AFh
1010
1
1
1
X
Table 7-4.
Read Byte SMBus Packet
S
Slave
Addres
s
Write
A
Comman
d Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 7-5.
Write Byte SMBus Packet
S
Slave Address
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1