IBM Intel Xeon X7350 44E4243 Data Sheet
Product codes
44E4243
Electrical Specifications
40
Document Number: 318080-002
2.12
Front Side Bus AC Specifications
The processor FSB timings specified in this section are defined at the
processor core (pads). Therefore, proper simulation of the FSB is the only
means to verify proper timing and signal quality.
processor core (pads). Therefore, proper simulation of the FSB is the only
means to verify proper timing and signal quality.
See
list the AC specifications associated with the processor FSB.
All AGTL+ timings are referenced to GTLREF_DATA_MID, GTLREF_DATA_END,
GTLREF_ADD_MID, and GTLREF_ADD_END for both ‘0’ and ‘1’ logic levels unless
otherwise specified.
GTLREF_ADD_MID, and GTLREF_ADD_END for both ‘0’ and ‘1’ logic levels unless
otherwise specified.
The timings specified in this section should be used in conjunction with the processor
signal integrity models provided by Intel. AGTL+ layout guidelines are also available in
the appropriate platform design guidelines.
signal integrity models provided by Intel. AGTL+ layout guidelines are also available in
the appropriate platform design guidelines.
Note:
Care should be taken to read all notes associated with a particular timing parameter.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The processor core clock frequency is derived from BCLK. The bus clock to processor core clock ratio is
determined during initialization as described in
includes core frequency to FSB
multipliers.
3.
The period specified here is the average period. A given period may vary from this specification as
governed by the period stability specification (T2).
4.
In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5.
Rise and fall times are measured single ended between 245 mV and 455 mV of the clock swing.
6.
Measured from -200 mV to +200 mV. The signal must be monotonic through the measurement region for
rise and fall time. The 400 mV measurement window is centered on the differential zero.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at nominal
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core
(pads).
4.
Valid delay timings for these signals are specified into the test circuit described in
GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * V
TT
.
Table 2-19. Front Side Bus Differential Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1
FSB Clock Frequency
265.247
266.745
MHz
T1: BCLK[1:0] Period
3.7489
3.7700
ns
T2: BCLK[1:0] Period Stability
N/A
150
ps
T3: BCLK[1:0] Rise Time
175
700
ps
T4: BCLK[1:0] Fall Time
175
700
ps
Differential Rising and Falling Edge Rates
0.6
4
V/ns
Table 2-20. Front Side Bus Common Clock AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 3
T10: Common Clock Output Valid Delay
0.22
1.10
ns
4
T11: Common Clock Input Setup Time
0.650
N/A
ns
5
T12: Common Clock Input Hold Time
0.150
N/A
ns
5
T13: RESET# Pulse Width
1
10
ms
6, 7, 8