IBM Intel Xeon X7350 44E4243 Data Sheet

Document Number: 318080-002

45

The following figures are used in conjunction with the AC timing tables, 

through 

.

For 

, the following apply:

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing 

Voltage (V

CROSS

) of the BCLK[1:0] at rising edge of BCLK0. All common clock 

AGTL+ signal timings are referenced at nominal GTLREF_DATA_MID, 

GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor 

core (pads).

2. All source synchronous AC timings for AGTL+ signals are referenced to their 

associated strobe (address or data) at nominal GTLREF_DATA_MID, 
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END. Source 
synchronous data signals are referenced to the falling edge of their associated data 
strobe. Source synchronous address signals are referenced to the rising and falling 
edge of their associated address strobe. All source synchronous AGTL+ signal 
timings are referenced at nominal GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID, and GTLREF_ADD_END at the processor core (pads).

3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V

CROSS

. All 

AGTL+ strobe signal timings are referenced at nominal GTLREF_DATA_MID, 
GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at the processor 
core (pads).

4. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V

TT

 at the 

processor pins. All TAP signal timings (TMS, TDI, etc...) are referenced at 0.5 * V

TT

 

at the processor core (pads).

5. All CMOS signal timings are referenced at 0.5 * V

TT

 at the processor pins.

6. All AC timings for the SMBus signals are referenced to the SM_CLK at 0.5 * 

SM_VCC at the processor pins. All SMBus signal timings (SM_DAT, SM_CLK, etc.) 
are referenced at 

The circuit used to test the AC specification is shown in 

.