IBM Intel Xeon E5430 43W3994 Data Sheet
Product codes
43W3994
Features
100
7.2.3
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no
later than 20 bus clocks after the response phase of the processor issued Stop Grant
Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon® Processor
5400 Series will issue two Stop Grant Acknowledge special bus cycles, one for each die.
Once the STPCLK# pin has been asserted, it may only be deasserted once the
processor is in the Stop Grant state. All processor cores will enter the Stop-Grant state
once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop
Grant state before the deassertion of STPCLK#.
later than 20 bus clocks after the response phase of the processor issued Stop Grant
Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon® Processor
5400 Series will issue two Stop Grant Acknowledge special bus cycles, one for each die.
Once the STPCLK# pin has been asserted, it may only be deasserted once the
processor is in the Stop Grant state. All processor cores will enter the Stop-Grant state
once the STPCLK# pin is asserted. Additionally, all processor cores must be in the Stop
Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to V
not be driven (allowing the level to return to V
TT
) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be
latched and can be serviced by software upon exit from the Stop Grant state.
latched and can be serviced by software upon exit from the Stop Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the front side bus (see
the front side bus (see
Figure 7-1. Stop Clock State Machine
Extended HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Normal State
Normal execution
Extended HALT Snoop or HALT
Snoop State
Snoop State
BCLK running
Service snoops to caches
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
RESET#, FSB interrupts
STPCLK#
Asserted
Asserted
STPCLK#
De-asserted
De-asserted
S
TP
C
LK
#
A
ss
er
te
d
S
TP
C
LK
#
D
e-
as
se
rte
d
Snoop Event Occurs
Snoop Event Serviced
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
HALT Bus Cycle Generated
Stop Grant Snoop State
BCLK running
Service snoops to caches
Service snoops to caches