Microchip Technology MCP6S26-I/P Linear IC PDIP-14 MCP6S26-I/P Data Sheet

Product codes
MCP6S26-I/P
Page of 42
 2003-2012 Microchip Technology Inc.
DS21117B-page 1
MCP6S21/2/6/8
Features
• Multiplexed Inputs: 1, 2, 6 or 8 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max)
• Low Offset: ±275 µV (max)
• High Bandwidth: 2 to 12 MHz (typ)
• Low Noise: 10 nV/
Hz @ 10 kHz (typ)
• Low Supply Current: 1.0 mA (typ)
• Single Supply: 2.5V to 5.5V
Typical Applications
• A/D Converter Driver
• Multiplexed Analog Applications
• Data Acquisition
• Industrial Instrumentation
• Test Equipment
• Medical Instrumentation
Package Types
Description
The Microchip Technology Inc. MCP6S21/2/6/8 are
analog Programmable Gain Amplifiers (PGA). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to eight chan-
nels through an SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support single
supply applications needing flexible performance or
multiple inputs.
The one channel MCP6S21 and the two channel
MCP6S22 are available in 8-pin PDIP, SOIC and
MSOP packages. The six channel MCP6S26 is avail-
able in 14-pin PDIP, SOIC and TSSOP packages. The
eight channel MCP6S28 is available in 16-pin PDIP
and SOIC packages. All parts are fully specified from
-40°C to +85°C.
Block Diagram
V
REF
CH0
V
SS
SI
SCK
1
2
3
4
8
7
6
5
V
DD
CS
V
OUT
CH1
CH0
CH2
CS
SI
1
2
3
4
14
13
12
11
V
REF
V
SS
V
OUT
5
6
7
10
9
8
CH3
SCK
V
DD
CH5
CH4
CH0
V
OUT
CH1
V
SS
CS
1
2
3
4
16
15
14
13 SI
SCK
5
6
7
12
11
10
CH2
CH4
CH7
V
DD
CH5
8
9
SO
CH6
CH3
SO
CH1
CH0
V
SS
SI
SCK
1
2
3
4
8
7
6
5
V
DD
CS
V
OUT
MCP6S21
PDIP, SOIC, MSOP
MCP6S26
PDIP, SOIC, TSSOP
MCP6S28
PDIP, SOIC
MCP6S22
PDIP, SOIC, MSOP
V
REF
 
V
OUT
V
REF
V
DD
CS
SI
SO
SCK
CH1
CH0
CH3
CH2
CH5
CH4
CH7
CH6
V
SS
8
R
F
R
G
MUX
SPI™
Logic
POR
Gain
Switches
+
-
R
e
sist
or Ladd
er (R
LA
D
)
Single-Ended, Rail-to-Rail I/O, Low Gain PGA