Intel Celeron M 380 RH80536NC0251M User Manual

Specification Update  

37 

The Specification Changes listed in this section apply to the following documents: 

•  Mobile Intel

(Document Number  251308) 

All Specification Changes will be incorporated into a future version of the appropriate mobile Intel 
Celeron processor on 0.13 micron process in Micro-FCPGA package documentation.  

IA32_MISC_ENABLE register, bit 24 status has changed from Reserved to the following definition: 

MSR Address:    

 

01A0h Accessed as a Qword 

Default Value:    

 

High Dword XXXX XXXXh 

                            

 

Low Dword XXXX XXXX XXXX XXXX XXXX XX00 X0X0 0001b 

Access: 

                

Read/Write  

Type: 

                

Shared 

IA32_MISC_ENABLE is a 64-bit register accessed only when referenced as a Qword through a 
RDMSR or WRMSR instruction. 

Bit 24 of the IA32_MISC_ENABLE status has changed from Reserved to the following: 

 

24 

L1 Data Cache Context Mode (R/W).  When set to a ‘1’ this bit places the L1 Data Cache into 
shared mode. When set to a ‘0’ (default) this bit places the L1 Data Cache into adaptive mode. 

When this bit is set to a ‘0’, adaptive mode, the Page Directory Base Register contained in CR3 
must be identical across all logical processors. 

Note: If the Context ID feature flag, ECX[10], is not set to a ‘1’ after executing the CPUID 
instruction with EAX = 1, then this feature is not supported and BIOS must not alter the contents 
of this bit location. 

In the CPUID instruction function 1 feature information, bit 10 of ECX register (ECX[10]) has been 
assigned flag to identify “Context ID feature” . The status has changed from Reserved to the following: 

10 

Context ID.  A value of 1 indicates the L1 data cache mode can be set to either adaptive 
mode or shared mode. A value of 0 indicates this feature is not supported.  

See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) 
for more details.