AMD Phenom 8650 Triple-Core HD8650WCGHBOX User Manual
Product codes
HD8650WCGHBOX
Product Errata
29
Revision Guide for AMD Family 10h Processors
41322
Rev. 3.16
February 2008
264 Incorrect DRAM Data Masks Asserted When DRAM Controller
Data Interleaving Is Enabled
Description
The processor may incorrectly assert the DRAM data masks for writes less than a cacheline when
DRAM controller data interleaving is enabled.
DRAM controller data interleaving is enabled.
Potential Effect on System
Data corruption.
Suggested Workaround
BIOS should set MSRC001_001F[36] (DisDatMsk) to 1b when F2x110[5] (DctDatIntLv) is set to 1b.
Fix Planned
Yes.